^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom Starfighter 2 DSA switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy_fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/if_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/b53.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "bcm_sf2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "bcm_sf2_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "b53/b53_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "b53/b53_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Return the number of active ports, not counting the IMP (CPU) port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int port, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (port = 0; port < ds->num_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (priv->port_sts[port].enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int ports_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Frequenty in Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const unsigned long rate_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 59220000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 60820000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 62500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 62500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ports_active = bcm_sf2_num_active_ports(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ports_active == 0 || !priv->clk_mdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* If we overflow our table, just use the recommended operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ports_active > ARRAY_SIZE(rate_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) new_rate = 90000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) new_rate = rate_table[ports_active - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clk_set_rate(priv->clk_mdiv, new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 reg, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Enable the port memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg &= ~P_TXQ_PSM_VDD(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Enable forwarding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Enable IMP port in dumb mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg = core_readl(priv, CORE_SWITCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg |= MII_DUMB_FWDG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) core_writel(priv, reg, CORE_SWITCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Configure Traffic Class to QoS mapping, allow each priority to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * to a different queue number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg |= i << (PRT_TO_QID_SHIFT * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) b53_brcm_hdr_setup(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (port == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (priv->type == BCM7445_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offset = CORE_STS_OVERRIDE_IMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) offset = CORE_STS_OVERRIDE_IMP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Force link status for IMP port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = core_readl(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg |= (MII_SW_OR | LINK_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg &= ~GMII_SPEED_UP_2G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) core_writel(priv, reg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg = core_readl(priv, CORE_IMP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg &= ~(RX_DIS | TX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) core_writel(priv, reg, CORE_IMP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg = core_readl(priv, CORE_G_PCTL_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg &= ~(RX_DIS | TX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) core_writel(priv, reg, CORE_G_PCTL_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) priv->port_sts[port].enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = reg_readl(priv, REG_SPHY_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg |= PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg_writel(priv, reg, REG_SPHY_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) udelay(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = reg_readl(priv, REG_SPHY_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg &= ~PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg_writel(priv, reg, REG_SPHY_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg |= CK25_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg_writel(priv, reg, REG_SPHY_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Use PHY-driven LED signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = reg_readl(priv, REG_LED_CNTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg |= SPDLNK_SRC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reg_writel(priv, reg, REG_LED_CNTRL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) off = P7_IRQ_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Port 0 interrupts are located on the first bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) off = P_IRQ_OFF(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) off = P7_IRQ_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Port 0 interrupts are located on the first bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) off = P_IRQ_OFF(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) intrl2_1_mask_set(priv, P_IRQ_MASK(off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct phy_device *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!dsa_is_user_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) priv->port_sts[port].enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bcm_sf2_recalc_clock(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Clear the memory power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg &= ~P_TXQ_PSM_VDD(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Enable Broadcom tags for that port if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (priv->brcm_tag_mask & BIT(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) b53_brcm_hdr_setup(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Configure Traffic Class to QoS mapping, allow each priority to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * to a different queue number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg |= i << (PRT_TO_QID_SHIFT * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Re-enable the GPHY and re-apply workarounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bcm_sf2_gphy_enable_set(ds, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* if phy_stop() has been called before, phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * will be in halted state, and phy_start()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * will call resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * the resume path does not configure back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * autoneg settings, and since we hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * the phy manually here, we need to reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * state machine also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) phy->state = PHY_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) phy_init_hw(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Enable MoCA port interrupts to get notified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (port == priv->moca_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bcm_sf2_port_intr_enable(priv, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Set per-queue pause threshold to 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Set ACB threshold to 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) reg = acb_readl(priv, ACB_QUEUE_CFG(port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SF2_NUM_EGRESS_QUEUES + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg &= ~XOFF_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) reg |= 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) acb_writel(priv, reg, ACB_QUEUE_CFG(port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SF2_NUM_EGRESS_QUEUES + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return b53_enable_port(ds, port, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Disable learning while in WoL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (priv->wol_ports_mask & (1 << port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg = core_readl(priv, CORE_DIS_LEARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reg |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) core_writel(priv, reg, CORE_DIS_LEARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (port == priv->moca_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bcm_sf2_port_intr_disable(priv, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bcm_sf2_gphy_enable_set(ds, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) b53_disable_port(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Power down the port memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg |= P_TXQ_PSM_VDD(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) priv->port_sts[port].enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bcm_sf2_recalc_clock(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) reg = reg_readl(priv, REG_SWITCH_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reg |= MDIO_MASTER_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg_writel(priv, reg, REG_SWITCH_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Page << 8 | offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) reg <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) core_writel(priv, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Page << 8 | offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg = 0x80 << 8 | regnum << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) reg <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = core_readl(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) core_writel(priv, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) reg = reg_readl(priv, REG_SWITCH_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) reg &= ~MDIO_MASTER_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) reg_writel(priv, reg, REG_SWITCH_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct bcm_sf2_priv *priv = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Intercept reads from Broadcom pseudo-PHY address, else, send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * them to our master MDIO bus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct bcm_sf2_priv *priv = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Intercept writes to the Broadcom pseudo-PHY address, else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * send them to our master MDIO bus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return mdiobus_write_nested(priv->master_mii_bus, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct dsa_switch *ds = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ~priv->irq0_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct dsa_switch *ds = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ~priv->irq1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) priv->port_sts[7].link = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dsa_port_phylink_mac_change(ds, 7, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) priv->port_sts[7].link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dsa_port_phylink_mac_change(ds, 7, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* The watchdog reset does not work on 7278, we need to hit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * "external" reset line through the reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = reset_control_assert(priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return reset_control_deassert(priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) reg = core_readl(priv, CORE_WATCHDOG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) core_writel(priv, reg, CORE_WATCHDOG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg = core_readl(priv, CORE_WATCHDOG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!(reg & SOFTWARE_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } while (timeout-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) intrl2_0_mask_set(priv, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) intrl2_1_mask_set(priv, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct device_node *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) phy_interface_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) priv->moca_port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for_each_available_child_of_node(dn, port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (of_property_read_u32(port, "reg", &port_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Internal PHYs get assigned a specific 'phy-mode' property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * value: "internal" to help flag them before MDIO probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * has completed, since they might be turned off at that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = of_get_phy_mode(port, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (mode == PHY_INTERFACE_MODE_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) priv->int_phy_mask |= 1 << port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (mode == PHY_INTERFACE_MODE_MOCA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) priv->moca_port = port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) priv->brcm_tag_mask |= 1 << port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Ensure that port 5 is not picked up as a DSA CPU port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * flavour but a regular port instead. We should be using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * devlink to be able to set the port flavour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) prop = of_find_property(port, "ethernet", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) of_remove_property(port, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int bcm_sf2_mdio_register(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct device_node *dn, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int err, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Find our integrated MDIO bus node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) priv->master_mii_bus = of_mdio_find_bus(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!priv->master_mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) get_device(&priv->master_mii_bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) priv->master_mii_dn = dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) priv->slave_mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!priv->slave_mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) priv->slave_mii_bus->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) priv->slave_mii_bus->name = "sf2 slave mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) index++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) priv->slave_mii_bus->dev.of_node = dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Include the pseudo-PHY address to divert reads towards our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * workaround. This is only required for 7445D0, since 7445E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * disconnects the internal switch pseudo-PHY such that we can use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * regular SWITCH_MDIO master controller instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Here we flag the pseudo PHY as needing special treatment and would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * otherwise make all other PHY read/writes go to the master MDIO bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * controller that comes with this switch backed by the "mdio-unimac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (of_machine_is_compatible("brcm,bcm7445d0"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) priv->indir_phy_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ds->phys_mii_mask = priv->indir_phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ds->slave_mii_bus = priv->slave_mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) priv->slave_mii_bus->parent = ds->dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* We need to make sure that of_phy_connect() will not work by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * removing the 'phandle' and 'linux,phandle' properties and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * unregister the existing PHY device that was already registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for_each_available_child_of_node(dn, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (of_property_read_u32(child, "reg", ®) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) reg >= PHY_MAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!(priv->indir_phy_mask & BIT(reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) prop = of_find_property(child, "phandle", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) of_remove_property(child, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) prop = of_find_property(child, "linux,phandle", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) of_remove_property(child, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) phydev = of_phy_find_device(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) phy_device_remove(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = mdiobus_register(priv->slave_mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (err && dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mdiobus_free(priv->slave_mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mdiobus_unregister(priv->slave_mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mdiobus_free(priv->slave_mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) of_node_put(priv->master_mii_dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* The BCM7xxx PHY driver expects to find the integrated PHY revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * in bits 15:8 and the patch level in bits 7:0 which is exactly what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * the REG_PHY_REVISION register layout is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (priv->int_phy_mask & BIT(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return priv->hw_params.gphy_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long *supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!phy_interface_mode_is_rgmii(state->interface) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) state->interface != PHY_INTERFACE_MODE_MII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) state->interface != PHY_INTERFACE_MODE_REVMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) state->interface != PHY_INTERFACE_MODE_GMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) state->interface != PHY_INTERFACE_MODE_INTERNAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) state->interface != PHY_INTERFACE_MODE_MOCA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (port != core_readl(priv, CORE_IMP0_PRT_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(ds->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "Unsupported interface: %d for port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) state->interface, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Allow all the expected bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) phylink_set(mask, Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) phylink_set_port_modes(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) phylink_set(mask, Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) phylink_set(mask, Asym_Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* With the exclusion of MII and Reverse MII, we support Gigabit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * including Half duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (state->interface != PHY_INTERFACE_MODE_MII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) state->interface != PHY_INTERFACE_MODE_REVMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) phylink_set(mask, 1000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) phylink_set(mask, 1000baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) phylink_set(mask, 10baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) phylink_set(mask, 10baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) phylink_set(mask, 100baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) phylink_set(mask, 100baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bitmap_and(supported, supported, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bitmap_and(state->advertising, state->advertising, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 id_mode_dis = 0, port_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (port == core_readl(priv, CORE_IMP0_PRT_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) switch (state->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) id_mode_dis = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) port_mode = EXT_GPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case PHY_INTERFACE_MODE_MII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) port_mode = EXT_EPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case PHY_INTERFACE_MODE_REVMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) port_mode = EXT_REVMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Nothing required for all other PHYs: internal and MoCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Clear id_mode_dis bit, and the existing port mode, let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * RGMII_MODE_EN bet set by mac_link_{up,down}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) reg &= ~ID_MODE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) reg |= port_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (id_mode_dis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reg |= ID_MODE_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) phy_interface_t interface, bool link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!phy_interface_mode_is_rgmii(interface) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) interface != PHY_INTERFACE_MODE_MII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) interface != PHY_INTERFACE_MODE_REVMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* If the link is down, just disable the interface to conserve power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg |= RGMII_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) reg &= ~RGMII_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 reg, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (priv->type == BCM7445_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reg = core_readl(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) reg &= ~LINK_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) core_writel(priv, reg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) bcm_sf2_sw_mac_link_set(ds, port, interface, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int speed, int duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) bool tx_pause, bool rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct ethtool_eee *p = &priv->dev->ports[port].eee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 reg, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) bcm_sf2_sw_mac_link_set(ds, port, interface, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (priv->type == BCM7445_DEVICE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (interface == PHY_INTERFACE_MODE_RGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) interface == PHY_INTERFACE_MODE_RGMII_TXID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) interface == PHY_INTERFACE_MODE_MII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) interface == PHY_INTERFACE_MODE_REVMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) reg |= TX_PAUSE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) reg |= RX_PAUSE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) reg = SW_OVERRIDE | LINK_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) reg |= SPDSTS_1000 << SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) reg |= SPDSTS_100 << SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) reg |= DUPLX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) core_writel(priv, reg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (mode == MLO_AN_PHY && phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) p->eee_enabled = b53_eee_init(ds, port, phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct phylink_link_state *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) status->link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* MoCA port is special as we do not get link status from CORE_LNKSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * which means that we need to force the link at the port override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * level to get the data to flow. We do use what the interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * did determine before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * For the other ports, we just force the link status, since this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * a fixed PHY device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (port == priv->moca_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) status->link = priv->port_sts[port].link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* For MoCA interfaces, also force a link down notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * since some version of the user-space daemon (mocad) use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * cmd->autoneg to force the link, which messes up the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * state machine and make it go in PHY_FORCING state instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!status->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) netif_carrier_off(dsa_to_port(ds, port)->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) status->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) status->link = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static void bcm_sf2_enable_acb(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Enable ACB globally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) reg = acb_readl(priv, ACB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) acb_writel(priv, reg, ACB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) reg |= ACB_EN | ACB_ALGORITHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) acb_writel(priv, reg, ACB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) bcm_sf2_intr_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Disable all ports physically present including the IMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * port, the other ones have already been disabled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * bcm_sf2_sw_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) for (port = 0; port < ds->num_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) bcm_sf2_port_disable(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!priv->wol_ports_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int bcm_sf2_sw_resume(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!priv->wol_ports_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = bcm_sf2_sw_rst(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pr_err("%s: failed to software reset switch\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = bcm_sf2_cfp_resume(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (priv->hw_params.num_gphy == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) bcm_sf2_gphy_enable_set(ds, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ds->ops->setup(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct ethtool_wolinfo pwol = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Get the parent device WoL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (p->ethtool_ops->get_wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) p->ethtool_ops->get_wol(p, &pwol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Advertise the parent device supported settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) wol->supported = pwol.supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) memset(&wol->sopass, 0, sizeof(wol->sopass));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (pwol.wolopts & WAKE_MAGICSECURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (priv->wol_ports_mask & (1 << port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) wol->wolopts = pwol.wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct ethtool_wolinfo pwol = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (p->ethtool_ops->get_wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) p->ethtool_ops->get_wol(p, &pwol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (wol->wolopts & ~pwol.supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (wol->wolopts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) priv->wol_ports_mask |= (1 << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) priv->wol_ports_mask &= ~(1 << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* If we have at least one port enabled, make sure the CPU port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * is also enabled. If the CPU port is the last one enabled, we disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * it since this configuration does not make sense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) priv->wol_ports_mask |= (1 << cpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) priv->wol_ports_mask &= ~(1 << cpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return p->ethtool_ops->set_wol(p, wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int bcm_sf2_sw_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Enable all valid ports and disable those unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) for (port = 0; port < priv->hw_params.num_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* IMP port receives special treatment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (dsa_is_user_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bcm_sf2_port_setup(ds, port, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) else if (dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) bcm_sf2_imp_setup(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) bcm_sf2_port_disable(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) b53_configure_vlan(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) bcm_sf2_enable_acb(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return b53_setup_devlink_resources(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dsa_devlink_resources_unregister(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* The SWITCH_CORE register space is managed by b53 but operates on a page +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * register basis so we need to translate that into an address that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * bus-glue understands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct bcm_sf2_priv *priv = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct b53_io_ops bcm_sf2_io_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .read8 = bcm_sf2_core_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .read16 = bcm_sf2_core_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .read32 = bcm_sf2_core_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .read48 = bcm_sf2_core_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .read64 = bcm_sf2_core_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .write8 = bcm_sf2_core_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .write16 = bcm_sf2_core_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .write32 = bcm_sf2_core_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .write48 = bcm_sf2_core_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .write64 = bcm_sf2_core_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 stringset, uint8_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) int cnt = b53_get_sset_count(ds, port, stringset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) b53_get_strings(ds, port, stringset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) bcm_sf2_cfp_get_strings(ds, port, stringset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) data + cnt * ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) uint64_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) b53_get_ethtool_stats(ds, port, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int cnt = b53_get_sset_count(ds, port, sset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (cnt < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const struct dsa_switch_ops bcm_sf2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .get_tag_protocol = b53_get_tag_protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .setup = bcm_sf2_sw_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .teardown = bcm_sf2_sw_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .get_strings = bcm_sf2_sw_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .get_sset_count = bcm_sf2_sw_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .get_phy_flags = bcm_sf2_sw_get_phy_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .phylink_validate = bcm_sf2_sw_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .phylink_mac_config = bcm_sf2_sw_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .phylink_fixed_state = bcm_sf2_sw_fixed_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .suspend = bcm_sf2_sw_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .resume = bcm_sf2_sw_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .get_wol = bcm_sf2_sw_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .set_wol = bcm_sf2_sw_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .port_enable = bcm_sf2_port_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .port_disable = bcm_sf2_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .get_mac_eee = b53_get_mac_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .set_mac_eee = b53_set_mac_eee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .port_bridge_join = b53_br_join,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .port_bridge_leave = b53_br_leave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .port_stp_state_set = b53_br_set_stp_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .port_fast_age = b53_br_fast_age,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .port_vlan_filtering = b53_vlan_filtering,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .port_vlan_prepare = b53_vlan_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .port_vlan_add = b53_vlan_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .port_vlan_del = b53_vlan_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .port_fdb_dump = b53_fdb_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .port_fdb_add = b53_fdb_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .port_fdb_del = b53_fdb_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .get_rxnfc = bcm_sf2_get_rxnfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .set_rxnfc = bcm_sf2_set_rxnfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .port_mirror_add = b53_mirror_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .port_mirror_del = b53_mirror_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .port_mdb_prepare = b53_mdb_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .port_mdb_add = b53_mdb_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .port_mdb_del = b53_mdb_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct bcm_sf2_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) const u16 *reg_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) unsigned int core_reg_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int num_cfp_rules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Register offsets for the SWITCH_REG_* block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const u16 bcm_sf2_7445_reg_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [REG_SWITCH_CNTRL] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [REG_SWITCH_STATUS] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [REG_DIR_DATA_WRITE] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [REG_DIR_DATA_READ] = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [REG_SWITCH_REVISION] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [REG_PHY_REVISION] = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [REG_SPHY_CNTRL] = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [REG_RGMII_0_CNTRL] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [REG_RGMII_1_CNTRL] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [REG_RGMII_2_CNTRL] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [REG_LED_0_CNTRL] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [REG_LED_1_CNTRL] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [REG_LED_2_CNTRL] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .type = BCM7445_DEVICE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .core_reg_align = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .reg_offsets = bcm_sf2_7445_reg_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .num_cfp_rules = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const u16 bcm_sf2_7278_reg_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [REG_SWITCH_CNTRL] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [REG_SWITCH_STATUS] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [REG_DIR_DATA_WRITE] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [REG_DIR_DATA_READ] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [REG_SWITCH_REVISION] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [REG_PHY_REVISION] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [REG_SPHY_CNTRL] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [REG_RGMII_0_CNTRL] = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [REG_RGMII_1_CNTRL] = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [REG_RGMII_2_CNTRL] = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [REG_LED_0_CNTRL] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [REG_LED_1_CNTRL] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [REG_LED_2_CNTRL] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .type = BCM7278_DEVICE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .core_reg_align = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .reg_offsets = bcm_sf2_7278_reg_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .num_cfp_rules = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct of_device_id bcm_sf2_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) { .compatible = "brcm,bcm7445-switch-v4.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .data = &bcm_sf2_7445_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { .compatible = "brcm,bcm7278-switch-v4.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .data = &bcm_sf2_7278_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { .compatible = "brcm,bcm7278-switch-v4.8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .data = &bcm_sf2_7278_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int bcm_sf2_sw_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) const struct of_device_id *of_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) const struct bcm_sf2_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct b53_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct dsa_switch_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct device_node *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct bcm_sf2_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct b53_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) void __iomem **base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u32 reg, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) of_id = of_match_node(bcm_sf2_of_match, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (!of_id || !of_id->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) priv->type = data->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) priv->reg_offsets = data->reg_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) priv->core_reg_align = data->core_reg_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) priv->num_cfp_rules = data->num_cfp_rules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return PTR_ERR(priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Auto-detection using standard registers will not work, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * provide an indication of what kind of device we are for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * b53_common to work with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) pdata->chip_id = priv->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ds = dev->ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ds->ops = &bcm_sf2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* Advertise the 8 egress queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_set_drvdata(&pdev->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) spin_lock_init(&priv->indir_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mutex_init(&priv->cfp.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) INIT_LIST_HEAD(&priv->cfp.rules_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* CFP rule #0 cannot be used for specific classifications, flag it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * permanently used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) set_bit(0, priv->cfp.used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) set_bit(0, priv->cfp.unique);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* Balance of_node_put() done by of_find_node_by_name() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) of_node_get(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ports = of_find_node_by_name(dn, "ports");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) bcm_sf2_identify_ports(priv, ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) of_node_put(ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) priv->irq0 = irq_of_parse_and_map(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) priv->irq1 = irq_of_parse_and_map(dn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) base = &priv->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) *base = devm_platform_ioremap_resource(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (IS_ERR(*base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pr_err("unable to find register: %s\n", reg_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return PTR_ERR(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) base++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (IS_ERR(priv->clk_mdiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ret = PTR_ERR(priv->clk_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) clk_prepare_enable(priv->clk_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = bcm_sf2_sw_rst(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pr_err("unable to software reset switch: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) goto out_clk_mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) bcm_sf2_gphy_enable_set(priv->dev->ds, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret = bcm_sf2_mdio_register(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) pr_err("failed to register MDIO bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) goto out_clk_mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) bcm_sf2_gphy_enable_set(priv->dev->ds, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = bcm_sf2_cfp_rst(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pr_err("failed to reset CFP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* Disable all interrupts and request them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) bcm_sf2_intr_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) "switch_0", ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pr_err("failed to request switch_0 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "switch_1", ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pr_err("failed to request switch_1 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Reset the MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) reg = core_readl(priv, CORE_GMNCFGCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) reg |= RST_MIB_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) core_writel(priv, reg, CORE_GMNCFGCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) reg &= ~RST_MIB_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) core_writel(priv, reg, CORE_GMNCFGCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Get the maximum number of ports for this switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (priv->hw_params.num_ports > DSA_MAX_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) priv->hw_params.num_ports = DSA_MAX_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* Assume a single GPHY setup if we can't read that property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (of_property_read_u32(dn, "brcm,num-gphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) &priv->hw_params.num_gphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) priv->hw_params.num_gphy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) rev = reg_readl(priv, REG_SWITCH_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SWITCH_TOP_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) priv->hw_params.core_rev = (rev & SF2_REV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) rev = reg_readl(priv, REG_PHY_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = b53_switch_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) goto out_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) priv->irq0, priv->irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) out_mdio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) bcm_sf2_mdio_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) out_clk_mdiv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) clk_disable_unprepare(priv->clk_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int bcm_sf2_sw_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) priv->wol_ports_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) bcm_sf2_intr_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dsa_unregister_switch(priv->dev->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) bcm_sf2_cfp_exit(priv->dev->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) bcm_sf2_mdio_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) clk_disable_unprepare(priv->clk_mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) reset_control_assert(priv->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* For a kernel about to be kexec'd we want to keep the GPHY on for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * successful MDIO bus scan to occur. If we did turn off the GPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * before (e.g: port_disable), this will also power it back on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * Do not rely on kexec_in_progress, just power the PHY on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (priv->hw_params.num_gphy == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) bcm_sf2_gphy_enable_set(priv->dev->ds, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static int bcm_sf2_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return dsa_switch_suspend(priv->dev->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int bcm_sf2_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return dsa_switch_resume(priv->dev->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) bcm_sf2_suspend, bcm_sf2_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static struct platform_driver bcm_sf2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .probe = bcm_sf2_sw_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .remove = bcm_sf2_sw_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .shutdown = bcm_sf2_sw_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = "brcm-sf2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .of_match_table = bcm_sf2_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .pm = &bcm_sf2_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) module_platform_driver(bcm_sf2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MODULE_AUTHOR("Broadcom Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) MODULE_ALIAS("platform:brcm-sf2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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