^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI HECC (CAN) device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This driver supports TI's HECC (High End CAN Controller module) and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * specs for the same is available at <http://www.ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed as is WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/can/rx-offload.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRV_NAME "ti_hecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HECC_MODULE_VERSION "0.7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_VERSION(HECC_MODULE_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* TX / RX Mailbox Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Important Note: TX mailbox configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * TX mailboxes should be restricted to the number of SKB buffers to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * maintaining SKB buffers separately. TX mailboxes should be a power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * for the mailbox logic to work. Top mailbox numbers are reserved for RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * and lower mailboxes for TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 4 (default) 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HECC_MB_TX_SHIFT 2 /* as per table above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* RX mailbox configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * The remaining mailboxes are used for reception and are delivered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * based on their timestamp, to avoid a hardware race when CANME is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * changed while CAN-bus traffic is being received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HECC_RX_LAST_MBOX (HECC_MAX_TX_MBOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* TI HECC module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HECC_CANME 0x0 /* Mailbox enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HECC_CANMD 0x4 /* Mailbox direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HECC_CANTRS 0x8 /* Transmit request set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HECC_CANTRR 0xC /* Transmit request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HECC_CANTA 0x10 /* Transmission acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HECC_CANAA 0x14 /* Abort acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HECC_CANRMP 0x18 /* Receive message pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HECC_CANRML 0x1C /* Receive message lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HECC_CANRFP 0x20 /* Remote frame pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HECC_CANMC 0x28 /* Master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HECC_CANBTC 0x2C /* Bit timing configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HECC_CANES 0x30 /* Error and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HECC_CANTEC 0x34 /* Transmit error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HECC_CANREC 0x38 /* Receive error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HECC_CANGIM 0x40 /* Global interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HECC_CANMIL 0x4C /* Mailbox interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HECC_CANOPC 0x50 /* Overwrite protection control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HECC_CANTIOC 0x54 /* Transmit I/O control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HECC_CANRIOC 0x58 /* Receive I/O control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HECC_CANLNT 0x5C /* HECC only: Local network time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* TI HECC RAM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HECC_CANMOTS 0x80 /* Message object time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Mailbox registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HECC_CANMID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HECC_CANMCF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HECC_CANMDL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HECC_CANMDH 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HECC_SET_REG 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HECC_CANMC_CCR BIT(12) /* Change config request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HECC_CANMC_SRES BIT(5) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HECC_CANMID_IDE BIT(31) /* Extended frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HECC_CANES_FE BIT(24) /* form error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HECC_CANES_BE BIT(23) /* bit error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HECC_CANES_CRCE BIT(21) /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HECC_CANES_SE BIT(20) /* stuff bit error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HECC_CANES_ACKE BIT(19) /* ack error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HECC_CANES_BO BIT(18) /* Bus off status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HECC_CANES_EP BIT(17) /* Error passive status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HECC_CANES_EW BIT(16) /* Error warning status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HECC_CANES_SMA BIT(5) /* suspend mode ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HECC_CANES_CCE BIT(4) /* Change config enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HECC_CANES_PDA BIT(3) /* Power down mode ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HECC_CANBTC_SAM BIT(7) /* sample points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) HECC_CANES_CRCE | HECC_CANES_SE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) HECC_CANES_ACKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HECC_CANES_FLAGS (HECC_BUS_ERROR | HECC_CANES_BO |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) HECC_CANES_EP | HECC_CANES_EW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* CAN Bittiming constants as per HECC specs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct can_bittiming_const ti_hecc_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .tseg1_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .tseg2_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .brp_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct ti_hecc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct can_priv can; /* MUST be first member/field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct can_rx_offload offload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *hecc_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *mbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool use_hecc1int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) spinlock_t mbx_lock; /* CANME register needs protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 tx_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct regulator *reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return priv->tx_head & HECC_TX_MB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return priv->tx_tail & HECC_TX_MB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __raw_writel(val, priv->hecc_ram + mbxno * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __raw_writel(val, priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return __raw_readl(priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 bit_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 bit_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct can_bittiming *bit_timing = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 can_btc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) & 0xF) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (bit_timing->brp > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) can_btc |= HECC_CANBTC_SAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) netdev_warn(priv->ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "WARN: Triple sampling not set due to h/w limitations");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* ERM being set to 0 by default meaning resync at falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hecc_write(priv, HECC_CANBTC, can_btc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!priv->reg_xceiver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return regulator_enable(priv->reg_xceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return regulator_disable(priv->reg_xceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void ti_hecc_reset(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) netdev_dbg(ndev, "resetting hecc ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Set change control request and wait till enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* INFO: It has been observed that at times CCE bit may not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * set and hw seems to be ok even if this bit is not set so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * timing out with a timing of 1ms to respect the specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cnt = HECC_CCE_WAIT_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) --cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Note: On HECC, BTC can be programmed only in initialization mode, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * it is expected that the can bittiming parameters are set via ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * utility before the device is opened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ti_hecc_set_btc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hecc_write(priv, HECC_CANMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* INFO: It has been observed that at times CCE bit may not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * set and hw seems to be ok even if this bit is not set so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cnt = HECC_CCE_WAIT_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) --cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Enable TX and RX I/O Control pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Clear registers for clean operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hecc_write(priv, HECC_CANTA, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) hecc_write(priv, HECC_CANME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hecc_write(priv, HECC_CANMD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* SCC compat mode NOT supported (and not needed too) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void ti_hecc_start(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 cnt, mbxno, mbx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* put HECC in initialization mode and set btc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ti_hecc_reset(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) priv->tx_head = HECC_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) priv->tx_tail = HECC_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Enable local and global acceptance mask registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Prepare configured mailboxes to receive messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mbx_mask = BIT(mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hecc_clear_bit(priv, HECC_CANME, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hecc_write_lam(priv, mbxno, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hecc_set_bit(priv, HECC_CANMD, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hecc_set_bit(priv, HECC_CANME, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Enable tx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Prevent message over-write to create a rx fifo, but not for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * the lowest priority mailbox, since that allows detecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * overflows instead of the hardware silently dropping the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mbx_mask = ~BIT(HECC_RX_LAST_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hecc_write(priv, HECC_CANOPC, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (priv->use_hecc1int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hecc_write(priv, HECC_CANMIL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) hecc_write(priv, HECC_CANGIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void ti_hecc_stop(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Disable the CPK; stop sending, erroring and acking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Disable interrupts and disable mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hecc_write(priv, HECC_CANGIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hecc_write(priv, HECC_CANMIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hecc_write(priv, HECC_CANME, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ti_hecc_start(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ti_hecc_get_berr_counter(const struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bec->txerr = hecc_read(priv, HECC_CANTEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) bec->rxerr = hecc_read(priv, HECC_CANREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* ti_hecc_xmit: HECC Transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * priority of the mailbox for transmission is dependent upon priority setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * field in mailbox registers. The mailbox with highest value in priority field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * is transmitted first. Only when two mailboxes have the same value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * priority field the highest numbered mailbox is transmitted first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * To utilize the HECC priority feature as described above we start with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * highest numbered mailbox with highest priority level and move on to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * mailbox with the same priority level and so on. Once we loop through all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * transmit mailboxes we choose the next priority level (lower) and so on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * until we reach the lowest priority level on the lowest numbered mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * when we stop transmission until all mailboxes are transmitted and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * restart at highest numbered mailbox with highest priority.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Two counters (head and tail) are used to track the next mailbox to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * and to track the echo buffer for already transmitted mailbox. The queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * is stopped when all the mailboxes are busy or when there is a priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * value roll-over happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct can_frame *cf = (struct can_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 mbxno, mbx_mask, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (can_dropped_invalid_skb(ndev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mbxno = get_tx_head_mb(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mbx_mask = BIT(mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spin_lock_irqsave(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spin_unlock_irqrestore(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) netdev_err(priv->ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) priv->tx_head, priv->tx_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_unlock_irqrestore(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Prepare mailbox for transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) data |= HECC_CANMCF_RTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else /* Standard frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data = (cf->can_id & CAN_SFF_MASK) << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hecc_write_mbx(priv, mbxno, HECC_CANMDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) be32_to_cpu(*(__be32 *)(cf->data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (cf->can_dlc > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hecc_write_mbx(priv, mbxno, HECC_CANMDH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) be32_to_cpu(*(__be32 *)(cf->data + 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *(u32 *)(cf->data + 4) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) can_put_echo_skb(skb, ndev, mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_lock_irqsave(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) --priv->tx_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hecc_set_bit(priv, HECC_CANME, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) spin_unlock_irqrestore(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hecc_write(priv, HECC_CANTRS, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return container_of(offload, struct ti_hecc_priv, offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int mbxno, u32 *timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) bool drop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 data, mbx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mbx_mask = BIT(mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (unlikely(drop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) skb = ERR_PTR(-ENOBUFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) goto mark_as_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) skb = alloc_can_skb(offload->dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) skb = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto mark_as_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (data & HECC_CANMID_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cf->can_id = (data >> 18) & CAN_SFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (data & HECC_CANMCF_RTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) cf->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cf->can_dlc = get_can_dlc(data & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *(__be32 *)(cf->data) = cpu_to_be32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (cf->can_dlc > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *timestamp = hecc_read_stamp(priv, mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Check for FIFO overrun.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * All but the last RX mailbox have activated overwrite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * protection. So skip check for overrun, if we're not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * handling the last RX mailbox.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * As the overwrite protection for the last RX mailbox is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * disabled, the CAN core might update while we're reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * it. This means the skb might be inconsistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Return an error to let rx-offload discard this CAN frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (unlikely(mbxno == HECC_RX_LAST_MBOX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hecc_read(priv, HECC_CANRML) & mbx_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) skb = ERR_PTR(-ENOBUFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mark_as_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hecc_write(priv, HECC_CANRMP, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int ti_hecc_error(struct net_device *ndev, int int_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (err_status & HECC_BUS_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* propagate the error condition to the can stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) skb = alloc_can_err_skb(ndev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) netdev_err(priv->ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "%s: alloc_can_err_skb() failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ++priv->can.can_stats.bus_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (err_status & HECC_CANES_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (err_status & HECC_CANES_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (err_status & HECC_CANES_SE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (err_status & HECC_CANES_CRCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (err_status & HECC_CANES_ACKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) cf->data[3] = CAN_ERR_PROT_LOC_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) timestamp = hecc_read(priv, HECC_CANLNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = can_rx_offload_queue_sorted(&priv->offload, skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ndev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void ti_hecc_change_state(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) enum can_state rx_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) enum can_state tx_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) skb = alloc_can_err_skb(priv->ndev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) priv->can.state = max(tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) can_change_state(priv->ndev, cf, tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) cf->data[6] = hecc_read(priv, HECC_CANTEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) cf->data[7] = hecc_read(priv, HECC_CANREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) timestamp = hecc_read(priv, HECC_CANLNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ndev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct net_device *ndev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct net_device_stats *stats = &ndev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 mbxno, mbx_mask, int_status, err_status, stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned long flags, rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int_status = hecc_read(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) priv->use_hecc1int ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) HECC_CANGIF1 : HECC_CANGIF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err_status = hecc_read(priv, HECC_CANES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (unlikely(err_status & HECC_CANES_FLAGS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ti_hecc_error(ndev, int_status, err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enum can_state rx_state, tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 rec = hecc_read(priv, HECC_CANREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 tec = hecc_read(priv, HECC_CANTEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (int_status & HECC_CANGIF_WLIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) handled |= HECC_CANGIF_WLIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) netdev_dbg(priv->ndev, "Error Warning interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ti_hecc_change_state(ndev, rx_state, tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (int_status & HECC_CANGIF_EPIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) handled |= HECC_CANGIF_EPIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) netdev_dbg(priv->ndev, "Error passive interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ti_hecc_change_state(ndev, rx_state, tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (int_status & HECC_CANGIF_BOIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) handled |= HECC_CANGIF_BOIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rx_state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tx_state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) netdev_dbg(priv->ndev, "Bus off interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hecc_write(priv, HECC_CANGIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) can_bus_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ti_hecc_change_state(ndev, rx_state, tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) enum can_state new_state, tx_state, rx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 rec = hecc_read(priv, HECC_CANREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 tec = hecc_read(priv, HECC_CANTEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (rec >= 128 || tec >= 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) new_state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else if (rec >= 96 || tec >= 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) new_state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) new_state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (new_state < priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rx_state = rec >= tec ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tx_state = rec <= tec ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ti_hecc_change_state(ndev, rx_state, tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (int_status & HECC_CANGIF_GMIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) while (priv->tx_tail - priv->tx_head > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mbxno = get_tx_tail_mb(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mbx_mask = BIT(mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) hecc_write(priv, HECC_CANTA, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) spin_lock_irqsave(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) hecc_clear_bit(priv, HECC_CANME, mbx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_unlock_irqrestore(&priv->mbx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) stamp = hecc_read_stamp(priv, mbxno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) stats->tx_bytes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) can_rx_offload_get_echo_skb(&priv->offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mbxno, stamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) can_led_event(ndev, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) --priv->tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* restart queue if wrap-up or if queue stalled on last pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if ((priv->tx_head == priv->tx_tail &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* offload RX mailboxes and let NAPI deliver them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) can_rx_offload_irq_offload_timestamp(&priv->offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rx_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* clear all interrupt conditions - read back to avoid spurious ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (priv->use_hecc1int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hecc_write(priv, HECC_CANGIF1, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int_status = hecc_read(priv, HECC_CANGIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) hecc_write(priv, HECC_CANGIF0, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int_status = hecc_read(priv, HECC_CANGIF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int ti_hecc_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ndev->name, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) netdev_err(ndev, "error requesting interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ti_hecc_transceiver_switch(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Open common can device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) err = open_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) netdev_err(ndev, "open_candev() failed %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ti_hecc_transceiver_switch(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) free_irq(ndev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) can_led_event(ndev, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ti_hecc_start(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) can_rx_offload_enable(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int ti_hecc_close(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) can_rx_offload_disable(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ti_hecc_stop(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) free_irq(ndev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) close_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ti_hecc_transceiver_switch(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) can_led_event(ndev, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const struct net_device_ops ti_hecc_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .ndo_open = ti_hecc_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .ndo_stop = ti_hecc_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .ndo_start_xmit = ti_hecc_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct of_device_id ti_hecc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .compatible = "ti,am3517-hecc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int ti_hecc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct net_device *ndev = (struct net_device *)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct ti_hecc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct resource *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct regulator *reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!IS_ENABLED(CONFIG_OF) || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) else if (IS_ERR(reg_xceiver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) reg_xceiver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(&pdev->dev, "alloc_candev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* handle hecc memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (IS_ERR(priv->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(&pdev->dev, "hecc ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) err = PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto probe_exit_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* handle hecc-ram memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "hecc-ram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (IS_ERR(priv->hecc_ram)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) err = PTR_ERR(priv->hecc_ram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto probe_exit_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* handle mbx memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (IS_ERR(priv->mbx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_err(&pdev->dev, "mbx ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) err = PTR_ERR(priv->mbx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto probe_exit_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(&pdev->dev, "No irq resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto probe_exit_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) priv->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) priv->reg_xceiver = reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) priv->can.bittiming_const = &ti_hecc_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) priv->can.do_set_mode = ti_hecc_do_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) spin_lock_init(&priv->mbx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ndev->irq = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ndev->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) platform_set_drvdata(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ndev->netdev_ops = &ti_hecc_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) priv->clk = clk_get(&pdev->dev, "hecc_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_err(&pdev->dev, "No clock available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) err = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) priv->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto probe_exit_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) priv->can.clock.freq = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto probe_exit_release_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) priv->offload.mailbox_read = ti_hecc_mailbox_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) priv->offload.mb_first = HECC_RX_FIRST_MBOX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) priv->offload.mb_last = HECC_RX_LAST_MBOX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) err = can_rx_offload_add_timestamp(ndev, &priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto probe_exit_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) err = register_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_err(&pdev->dev, "register_candev() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto probe_exit_offload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) devm_can_led_init(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) priv->base, (u32)ndev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) probe_exit_offload:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) can_rx_offload_del(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) probe_exit_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) probe_exit_release_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) probe_exit_candev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) free_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int ti_hecc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct ti_hecc_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unregister_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) can_rx_offload_del(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) free_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct ti_hecc_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) priv->can.state = CAN_STATE_SLEEPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int ti_hecc_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct ti_hecc_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define ti_hecc_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define ti_hecc_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* TI HECC netdevice driver: platform driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static struct platform_driver ti_hecc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .of_match_table = ti_hecc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .probe = ti_hecc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .remove = ti_hecc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .suspend = ti_hecc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .resume = ti_hecc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) module_platform_driver(ti_hecc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) MODULE_DESCRIPTION(DRV_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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