^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Peter Chen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Gerhard Bertelsmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Parts of this software are based on (derived from) the SJA1000 code by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2002-2007 Volkswagen Group Electronic Research
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 38106 Braunschweig, GERMANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 3. Neither the name of Volkswagen nor the names of its contributors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * may be used to endorse or promote products derived from this software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Alternatively, provided that this notice is retained in full, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * software may be distributed under the terms of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Public License ("GPL") version 2, in which case the provisions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * GPL apply INSTEAD OF those given above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The provided data structures and external interfaces from this code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * are not restricted to be used by modules with a GPL compatible license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/can.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRV_NAME "sun4i_can"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Registers address (physical base address 0x01C2BC00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Controller Register Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* mode select register (r/w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * offset:0x0000 default:0x0000_0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SUN4I_MSEL_WAKE_UP (0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SUN4I_MSEL_LOOPBACK_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SUN4I_MSEL_RESET_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* command register (w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * offset:0x0004 default:0x0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SUN4I_CMD_BUS_OFF_REQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SUN4I_CMD_SELF_RCV_REQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SUN4I_CMD_RELEASE_RBUF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SUN4I_CMD_ABORT_REQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SUN4I_CMD_TRANS_REQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* status register (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * offset:0x0008 default:0x0000_003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SUN4I_STA_BIT_ERR (0x00 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SUN4I_STA_FORM_ERR (0x01 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUN4I_STA_STUFF_ERR (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SUN4I_STA_OTHER_ERR (0x03 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SUN4I_STA_MASK_ERR (0x03 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SUN4I_STA_ERR_DIR BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SUN4I_STA_ERR_SEG_CODE (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SUN4I_STA_START (0x03 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SUN4I_STA_ID28_21 (0x02 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SUN4I_STA_ID20_18 (0x06 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUN4I_STA_SRTR (0x04 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SUN4I_STA_IDE (0x05 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SUN4I_STA_ID17_13 (0x07 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SUN4I_STA_ID12_5 (0x0f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SUN4I_STA_ID4_0 (0x0e << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SUN4I_STA_RTR (0x0c << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SUN4I_STA_RB1 (0x0d << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SUN4I_STA_RB0 (0x09 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SUN4I_STA_DLEN (0x0b << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SUN4I_STA_DATA_FIELD (0x0a << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SUN4I_STA_CRC_SEQUENCE (0x08 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SUN4I_STA_CRC_DELIMITER (0x18 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SUN4I_STA_ACK (0x19 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SUN4I_STA_ACK_DELIMITER (0x1b << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SUN4I_STA_END (0x1a << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SUN4I_STA_INTERMISSION (0x12 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SUN4I_STA_ACTIVE_ERROR (0x11 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SUN4I_STA_ERROR_DELIMITER (0x17 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SUN4I_STA_OVERLOAD (0x1c << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SUN4I_STA_BUS_OFF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SUN4I_STA_ERR_STA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SUN4I_STA_TRANS_BUSY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SUN4I_STA_RCV_BUSY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SUN4I_STA_TRANS_OVER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SUN4I_STA_TBUF_RDY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SUN4I_STA_DATA_ORUN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SUN4I_STA_RBUF_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* interrupt register (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * offset:0x000c default:0x0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SUN4I_INT_BUS_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SUN4I_INT_ARB_LOST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SUN4I_INT_ERR_PASSIVE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SUN4I_INT_WAKEUP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SUN4I_INT_DATA_OR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SUN4I_INT_ERR_WRN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SUN4I_INT_TBUF_VLD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SUN4I_INT_RBUF_VLD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* interrupt enable register (r/w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * offset:0x0010 default:0x0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SUN4I_INTEN_BERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SUN4I_INTEN_ARB_LOST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SUN4I_INTEN_ERR_PASSIVE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SUN4I_INTEN_WAKEUP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SUN4I_INTEN_OR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SUN4I_INTEN_ERR_WRN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SUN4I_INTEN_TX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SUN4I_INTEN_RX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SUN4I_ERR_INRCV (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SUN4I_ERR_INTRANS (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* filter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SUN4I_FILTER_CLOSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SUN4I_SINGLE_FLTER_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SUN4I_DUAL_FILTER_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* message buffer flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SUN4I_MSG_EFF_FLAG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SUN4I_MSG_RTR_FLAG BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* max. number of interrupts handled in ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SUN4I_CAN_MAX_IRQ 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SUN4I_MODE_MAX_RETRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct sun4ican_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct can_priv can;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct can_bittiming_const sun4ican_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .tseg1_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .tseg2_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .brp_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irqsave(&priv->cmdreg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel(val, priv->base + SUN4I_REG_CMD_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int set_normal_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int retry = SUN4I_MODE_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 mod_reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mod_reg_val &= ~SUN4I_MSEL_RESET_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) netdev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "setting controller into normal mode failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int set_reset_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int retry = SUN4I_MODE_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 mod_reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mod_reg_val |= SUN4I_MSEL_RESET_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SUN4I_MSEL_RESET_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) netdev_err(dev, "setting controller into reset mode failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* bittiming is called in reset_mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int sun4ican_set_bittiming(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cfg = ((bt->brp - 1) & 0x3FF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (((bt->sjw - 1) & 0x3) << 14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (((bt->phase_seg2 - 1) & 0x7) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cfg |= 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int sun4ican_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) netdev_err(dev, "could not enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) errors = readl(priv->base + SUN4I_REG_ERRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bec->txerr = errors & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bec->rxerr = (errors >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int sun4i_can_start(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 mod_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* we need to enter the reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err = set_reset_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) netdev_err(dev, "could not enter reset mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* set filters - we accept all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* clear error counters and error code capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(0xFF & ~SUN4I_INTEN_BERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) priv->base + SUN4I_REG_INTEN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* enter the selected mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = sun4ican_set_bittiming(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* we are ready to enter the normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = set_normal_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) netdev_err(dev, "could not enter normal mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int sun4i_can_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* we need to enter reset mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) err = set_reset_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) netdev_err(dev, "could not enter reset mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err = sun4i_can_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) netdev_err(dev, "starting CAN controller failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (netif_queue_stopped(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* transmit a CAN message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * message layout in the sk_buff should be like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * xx xx xx xx ff ll 00 11 22 33 44 55 66 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * [ can_id ] [flags] [len] [can data (up to 8 bytes]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct can_frame *cf = (struct can_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 dreg, msg_flag_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) canid_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (can_dropped_invalid_skb(dev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) id = cf->can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dlc = cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msg_flag_n = dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (id & CAN_RTR_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msg_flag_n |= SUN4I_MSG_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (id & CAN_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msg_flag_n |= SUN4I_MSG_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dreg = SUN4I_REG_BUF5_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dreg = SUN4I_REG_BUF3_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < dlc; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) writel(cf->data[i], priv->base + (dreg + i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) can_put_echo_skb(skb, dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static void sun4i_can_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) canid_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* create zero'ed CAN frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) skb = alloc_can_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fi = readl(priv->base + SUN4I_REG_BUF0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cf->can_dlc = get_can_dlc(fi & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (fi & SUN4I_MSG_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dreg = SUN4I_REG_BUF5_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) id |= CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dreg = SUN4I_REG_BUF3_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* remote frame ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (fi & SUN4I_MSG_RTR_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (i = 0; i < cf->can_dlc; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cf->data[i] = readl(priv->base + dreg + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cf->can_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) can_led_event(dev, CAN_LED_EVENT_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) enum can_state state = priv->can.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum can_state rx_state, tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int rxerr, txerr, errc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 ecc, alc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* we don't skip if alloc fails because we want the stats anyhow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) errc = readl(priv->base + SUN4I_REG_ERRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rxerr = (errc >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) txerr = errc & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cf->data[6] = txerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cf->data[7] = rxerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (isrc & SUN4I_INT_DATA_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* data overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) netdev_dbg(dev, "data overrun interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (likely(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) stats->rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* reset the CAN IP by entering reset mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * ignoring timeout error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) set_reset_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) set_normal_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* clear bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (isrc & SUN4I_INT_ERR_WRN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* error warning interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) netdev_dbg(dev, "error warning interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (status & SUN4I_STA_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) else if (status & SUN4I_STA_ERR_STA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (isrc & SUN4I_INT_BUS_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* bus error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) netdev_dbg(dev, "bus error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (likely(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ecc = readl(priv->base + SUN4I_REG_STA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) switch (ecc & SUN4I_STA_MASK_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case SUN4I_STA_BIT_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case SUN4I_STA_FORM_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case SUN4I_STA_STUFF_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* error occurred during transmission? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if ((ecc & SUN4I_STA_ERR_DIR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cf->data[2] |= CAN_ERR_PROT_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (isrc & SUN4I_INT_ERR_PASSIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* error passive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) netdev_dbg(dev, "error passive interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (state == CAN_STATE_ERROR_PASSIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (isrc & SUN4I_INT_ARB_LOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* arbitration lost interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) netdev_dbg(dev, "arbitration lost interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) alc = readl(priv->base + SUN4I_REG_STA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) priv->can.can_stats.arbitration_lost++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (likely(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cf->can_id |= CAN_ERR_LOSTARB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cf->data[0] = (alc >> 8) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (state != priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tx_state = txerr >= rxerr ? state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rx_state = txerr <= rxerr ? state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (likely(skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) can_change_state(dev, cf, tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) priv->can.state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (state == CAN_STATE_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) can_bus_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (likely(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct net_device *dev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 isrc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (n < SUN4I_CAN_MAX_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) status = readl(priv->base + SUN4I_REG_STA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (isrc & SUN4I_INT_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) netdev_warn(dev, "wakeup interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (isrc & SUN4I_INT_TBUF_VLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* transmission complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) stats->tx_bytes +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) readl(priv->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SUN4I_REG_RBUF_RBACK_START_ADDR) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) can_get_echo_skb(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) can_led_event(dev, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if ((isrc & SUN4I_INT_RBUF_VLD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) !(isrc & SUN4I_INT_DATA_OR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* receive interrupt - don't read if overrun occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) while (status & SUN4I_STA_RBUF_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* RX buffer is not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) sun4i_can_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) status = readl(priv->base + SUN4I_REG_STA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (isrc &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (sun4i_can_err(dev, isrc, status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) readl(priv->base + SUN4I_REG_INT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (n >= SUN4I_CAN_MAX_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) netdev_dbg(dev, "%d messages handled in ISR", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return (n) ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int sun4ican_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* common open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err = open_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* register interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) netdev_err(dev, "request_irq err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto exit_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* turn on clocking for CAN peripheral block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) netdev_err(dev, "could not enable CAN peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto exit_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) err = sun4i_can_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) netdev_err(dev, "could not start CAN peripheral\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) goto exit_can_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) can_led_event(dev, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) exit_can_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) exit_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) exit_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int sun4ican_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct sun4ican_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sun4i_can_stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) can_led_event(dev, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct net_device_ops sun4ican_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ndo_open = sun4ican_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .ndo_stop = sun4ican_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .ndo_start_xmit = sun4ican_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct of_device_id sun4ican_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {.compatible = "allwinner,sun4i-a10-can"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_DEVICE_TABLE(of, sun4ican_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int sun4ican_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int sun4ican_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct sun4ican_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(&pdev->dev, "unable to request clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (IS_ERR(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err = PTR_ERR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev = alloc_candev(sizeof(struct sun4ican_priv), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "could not allocate memory for CAN device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev->netdev_ops = &sun4ican_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) priv->can.clock.freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) priv->can.bittiming_const = &sun4ican_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) priv->can.do_set_mode = sun4ican_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) priv->can.do_get_berr_counter = sun4ican_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) CAN_CTRLMODE_LISTENONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) CAN_CTRLMODE_LOOPBACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) CAN_CTRLMODE_3_SAMPLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) priv->base = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) priv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) spin_lock_init(&priv->cmdreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) err = register_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) DRV_NAME, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) devm_can_led_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) priv->base, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) exit_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static struct platform_driver sun4i_can_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .of_match_table = sun4ican_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .probe = sun4ican_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .remove = sun4ican_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) module_platform_driver(sun4i_can_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags