^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * MCP2510 support and bug fixes by Christian Pellegrin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * <chripell@evolware.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009 Christian Pellegrin EVOL S.r.l.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Written under contract by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Chris Elston, Katalix Systems, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Based on Microchip MCP251x CAN controller driver written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Based on CAN bus driver for the CCAN controller written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Simon Kallweit, intefo AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright 2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/can/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* SPI interface instruction set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define INSTRUCTION_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INSTRUCTION_READ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INSTRUCTION_BIT_MODIFY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define INSTRUCTION_RESET 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTS_TXB0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTS_TXB1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTS_TXB2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MPC251x registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BFPCTRL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define BFPCTRL_B0BFM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define BFPCTRL_B1BFM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define BFPCTRL_BFM_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define BFPCTRL_B0BFE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define BFPCTRL_B1BFE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define BFPCTRL_BFE_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define BFPCTRL_B0BFS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define BFPCTRL_B1BFS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define BFPCTRL_BFS_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TXRTSCTRL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define TXRTSCTRL_B0RTSM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define TXRTSCTRL_B1RTSM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define TXRTSCTRL_B2RTSM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define TXRTSCTRL_B0RTS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define TXRTSCTRL_B1RTS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define TXRTSCTRL_B2RTS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CANSTAT 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CANCTRL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define CANCTRL_REQOP_MASK 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define CANCTRL_REQOP_CONF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define CANCTRL_REQOP_LISTEN_ONLY 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define CANCTRL_REQOP_LOOPBACK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define CANCTRL_REQOP_SLEEP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define CANCTRL_REQOP_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define CANCTRL_OSM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define CANCTRL_ABAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEC 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REC 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CNF1 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define CNF1_SJW_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CNF2 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define CNF2_BTLMODE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define CNF2_SAM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define CNF2_PS1_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CNF3 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define CNF3_SOF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define CNF3_WAKFIL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) # define CNF3_PHSEG2_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CANINTE 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) # define CANINTE_MERRE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) # define CANINTE_WAKIE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define CANINTE_ERRIE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define CANINTE_TX2IE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define CANINTE_TX1IE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define CANINTE_TX0IE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define CANINTE_RX1IE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define CANINTE_RX0IE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CANINTF 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define CANINTF_MERRF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define CANINTF_WAKIF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # define CANINTF_ERRIF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # define CANINTF_TX2IF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # define CANINTF_TX1IF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) # define CANINTF_TX0IF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define CANINTF_RX1IF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define CANINTF_RX0IF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define CANINTF_ERR (CANINTF_ERRIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EFLG 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define EFLG_EWARN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define EFLG_RXWAR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define EFLG_TXWAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define EFLG_RXEP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define EFLG_TXEP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define EFLG_TXBO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define EFLG_RX0OVR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define EFLG_RX1OVR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define TXBCTRL_ABTF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define TXBCTRL_MLOA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define TXBCTRL_TXERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define TXBCTRL_TXREQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define SIDH_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define SIDL_SID_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define SIDL_SID_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) # define SIDL_EXIDE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define SIDL_EID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define SIDL_EID_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define DLC_RTR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TXBCTRL_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TXBSIDH_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TXBSIDL_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TXBEID8_OFF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TXBEID0_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TXBDLC_OFF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TXBDAT_OFF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define RXBCTRL_BUKT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define RXBCTRL_RXM0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define RXBCTRL_RXM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define RXBSIDH_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define RXBSIDL_IDE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define RXBSIDL_SRR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define RXBSIDL_EID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define RXBSIDL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define RXBDLC_LEN_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define RXBDLC_RTR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RXBCTRL_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RXBSIDH_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RXBSIDL_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RXBEID8_OFF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RXBEID0_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RXBDLC_OFF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RXBDAT_OFF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RXFSID(n) ((n < 3) ? 0 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RXMSIDH(n) ((n) * 4 + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RXMSIDL(n) ((n) * 4 + 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RXMEID8(n) ((n) * 4 + 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RXMEID0(n) ((n) * 4 + 0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GET_BYTE(val, byte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (((val) >> ((byte) * 8)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SET_BYTE(val, byte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (((val) & 0xff) << ((byte) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Buffer size required for the largest SPI transfer (i.e., reading a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CAN_FRAME_MAX_DATA_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CAN_FRAME_MAX_BITS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TX_ECHO_SKB_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MCP251X_OST_DELAY_MS (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DEVICE_NAME "mcp251x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct can_bittiming_const mcp251x_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .tseg1_min = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .brp_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum mcp251x_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CAN_MCP251X_MCP2510 = 0x2510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CAN_MCP251X_MCP2515 = 0x2515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CAN_MCP251X_MCP25625 = 0x25625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mcp251x_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct can_priv can;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct net_device *net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum mcp251x_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct mutex mcp_lock; /* SPI device lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 *spi_tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 *spi_rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct work_struct tx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct work_struct restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int force_quit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int after_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AFTER_SUSPEND_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AFTER_SUSPEND_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AFTER_SUSPEND_POWER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AFTER_SUSPEND_RESTART 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int restart_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct regulator *power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct regulator *transceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 reg_bfpctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MCP251X_IS(_model) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline int mcp251x_is_##_model(struct spi_device *spi) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mcp251x_priv *priv = spi_get_drvdata(spi); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return priv->model == CAN_MCP251X_MCP##_model; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MCP251X_IS(2510);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void mcp251x_clean(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (priv->tx_skb || priv->tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) net->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_kfree_skb(priv->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (priv->tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) can_free_echo_skb(priv->net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Note about handling of error return of mcp251x_spi_trans: accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * registers via SPI is not really different conceptually than using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * normal I/O assembler instructions, although it's much more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * complicated from a practical POV. So it's not advisable to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * check the return value of this function. Imagine that every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * error();", it would be a great mess (well there are some situation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * when exception handling C++ like could be useful after all). So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * just check that transfers are OK at the beginning of our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * conversation with the chip and to avoid doing really nasty things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * (like injecting bogus packets in the network stack).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int mcp251x_spi_trans(struct spi_device *spi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct spi_transfer t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .tx_buf = priv->spi_tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .rx_buf = priv->spi_rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .cs_change = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int mcp251x_spi_write(struct spi_device *spi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = spi_write(spi, priv->spi_tx_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) priv->spi_tx_buf[0] = INSTRUCTION_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) priv->spi_tx_buf[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mcp251x_spi_trans(spi, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val = priv->spi_rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) priv->spi_tx_buf[0] = INSTRUCTION_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) priv->spi_tx_buf[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 val[2] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *v1 = val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *v2 = val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mcp251x_spi_trans(spi, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *v1 = priv->spi_rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *v2 = priv->spi_rx_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) priv->spi_tx_buf[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) priv->spi_tx_buf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mcp251x_spi_write(spi, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) priv->spi_tx_buf[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) priv->spi_tx_buf[2] = v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) priv->spi_tx_buf[3] = v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mcp251x_spi_write(spi, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) priv->spi_tx_buf[1] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) priv->spi_tx_buf[2] = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) priv->spi_tx_buf[3] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mcp251x_spi_write(spi, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static u8 mcp251x_read_stat(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) delay_us, timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MCP251X_GPIO_TX0RTS = 0, /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MCP251X_GPIO_TX1RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MCP251X_GPIO_TX2RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MCP251X_GPIO_RX0BF, /* outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MCP251X_GPIO_RX1BF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MCP251X_GPIO_INPUT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MCP251X_GPIO_OUTPUT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const char * const mcp251x_gpio_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [MCP251X_GPIO_TX1RTS] = "TX1RTS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [MCP251X_GPIO_TX2RTS] = "TX2RTS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [MCP251X_GPIO_RX1BF] = "RX1BF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline bool mcp251x_gpio_is_input(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return offset <= MCP251X_GPIO_TX2RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int mcp251x_gpio_request(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* nothing to be done for inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (mcp251x_gpio_is_input(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) priv->reg_bfpctrl |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static void mcp251x_gpio_free(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* nothing to be done for inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (mcp251x_gpio_is_input(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) priv->reg_bfpctrl &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (mcp251x_gpio_is_input(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return GPIOF_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return GPIOF_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (mcp251x_gpio_is_input(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) reg = TXRTSCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mask = TXRTSCTRL_RTS(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) reg = BFPCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val = mcp251x_read_reg(priv->spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned long *maskp, unsigned long *bitsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val = mcp251x_read_reg(priv->spi, BFPCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val = FIELD_GET(BFPCTRL_BFS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bitsp[0] = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val = value ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv->reg_bfpctrl &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) priv->reg_bfpctrl |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mcp251x_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) unsigned long *maskp, unsigned long *bitsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct mcp251x_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) priv->reg_bfpctrl &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) priv->reg_bfpctrl |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void mcp251x_gpio_restore(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct gpio_chip *gpio = &priv->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!device_property_present(&priv->spi->dev, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) gpio->label = priv->spi->modalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gpio->parent = &priv->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gpio->request = mcp251x_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) gpio->free = mcp251x_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gpio->get_direction = mcp251x_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gpio->get = mcp251x_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) gpio->get_multiple = mcp251x_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) gpio->set = mcp251x_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gpio->set_multiple = mcp251x_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) gpio->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) gpio->names = mcp251x_gpio_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) gpio->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) gpio->of_node = priv->spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static inline void mcp251x_gpio_restore(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int len, int tx_buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (mcp251x_is_2510(spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 1; i < TXBDAT_OFF + len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mcp251x_spi_write(spi, TXBDAT_OFF + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int tx_buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 sid, eid, exide, rtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 buf[SPI_TRANSFER_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (exide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) sid = (frame->can_id & CAN_EFF_MASK) >> 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (exide << SIDL_EXIDE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mcp251x_spi_write(priv->spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (mcp251x_is_2510(spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 1; i < RXBDAT_OFF; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) for (; i < (RXBDAT_OFF + len); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spi_write_then_read(spi, priv->spi_tx_buf, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) priv->spi_rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SPI_TRANSFER_BUF_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) memcpy(buf + 1, priv->spi_rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) SPI_TRANSFER_BUF_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 buf[SPI_TRANSFER_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) skb = alloc_can_skb(priv->net, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(&spi->dev, "cannot allocate RX skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) priv->net->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mcp251x_hw_rx_frame(spi, buf, buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Extended ID format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) frame->can_id = CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) frame->can_id |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Extended ID part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SET_BYTE(buf[RXBEID8_OFF], 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SET_BYTE(buf[RXBEID0_OFF], 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Standard ID part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Remote transmission request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (buf[RXBDLC_OFF] & RXBDLC_RTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) frame->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Standard ID format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) frame->can_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) frame->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) priv->net->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) priv->net->stats.rx_bytes += frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) can_led_event(priv->net, CAN_LED_EVENT_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void mcp251x_hw_sleep(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* May only be called when device is sleeping! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int mcp251x_hw_wake(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Force wakeup interrupt to wake device, but don't execute IST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Wait for oscillator startup timer after wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mdelay(MCP251X_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Put device into config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Wait for the device to enter config mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MCP251X_OST_DELAY_MS * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Disable and clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) enable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (priv->tx_skb || priv->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (can_dropped_invalid_skb(net, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) netif_stop_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) priv->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) queue_work(priv->wq, &priv->tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mcp251x_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* We have to delay work since SPI I/O may sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) priv->restart_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (priv->can.restart_ms == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) priv->after_suspend = AFTER_SUSPEND_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) queue_work(priv->wq, &priv->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int mcp251x_set_normal_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mcp251x_write_reg(spi, CANINTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Put device into loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Put device into listen-only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Put device into normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Wait for the device to enter normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MCP251X_OST_DELAY_MS * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int mcp251x_do_set_bittiming(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (bt->brp - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) CNF2_SAM : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) (bt->prop_seg - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) (bt->phase_seg2 - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mcp251x_read_reg(spi, CNF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mcp251x_read_reg(spi, CNF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mcp251x_read_reg(spi, CNF3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mcp251x_do_set_bittiming(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) mcp251x_write_reg(spi, RXBCTRL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) mcp251x_write_reg(spi, RXBCTRL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) RXBCTRL_RXM0 | RXBCTRL_RXM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int mcp251x_hw_reset(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Wait for oscillator startup timer after power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mdelay(MCP251X_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) priv->spi_tx_buf[0] = INSTRUCTION_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = mcp251x_spi_write(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Wait for oscillator startup timer after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) mdelay(MCP251X_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Wait for reset to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MCP251X_OST_DELAY_MS * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int mcp251x_hw_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = mcp251x_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ctrl = mcp251x_read_reg(spi, CANCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Check for power up default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if ((ctrl & 0x17) != 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int mcp251x_power_enable(struct regulator *reg, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (IS_ERR_OR_NULL(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return regulator_enable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return regulator_disable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int mcp251x_stop(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) close_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Disable and clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mcp251x_write_reg(spi, TXBCTRL(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mcp251x_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mcp251x_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) can_led_event(net, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) skb = alloc_can_err_skb(net, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) frame->can_id |= can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) frame->data[1] = data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) netdev_err(net, "cannot allocate error skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void mcp251x_tx_work_handler(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (priv->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (priv->can.state == CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mcp251x_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) frame = (struct can_frame *)priv->tx_skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) mcp251x_hw_tx(spi, frame, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) priv->tx_len = 1 + frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) can_put_echo_skb(priv->tx_skb, net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void mcp251x_restart_work_handler(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (priv->after_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (priv->after_suspend & AFTER_SUSPEND_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mcp251x_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) mcp251x_setup(net, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mcp251x_gpio_restore(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mcp251x_hw_wake(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mcp251x_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) netif_device_attach(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mcp251x_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mcp251x_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) priv->after_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (priv->restart_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) priv->restart_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mcp251x_write_reg(spi, TXBCTRL(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mcp251x_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct mcp251x_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) while (!priv->force_quit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) enum can_state new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 intf, eflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u8 clear_intf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int can_id = 0, data1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* mask out flags we don't care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* receive buffer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (intf & CANINTF_RX0IF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mcp251x_hw_rx(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Free one buffer ASAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * (The MCP2515/25625 does this automatically.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (mcp251x_is_2510(spi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mcp251x_write_bits(spi, CANINTF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) CANINTF_RX0IF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* receive buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (intf & CANINTF_RX1IF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mcp251x_hw_rx(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* The MCP2515/25625 does this automatically. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (mcp251x_is_2510(spi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) clear_intf |= CANINTF_RX1IF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* any error or tx interrupt we need to clear? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (intf & (CANINTF_ERR | CANINTF_TX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (clear_intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mcp251x_write_bits(spi, EFLG, eflag, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Update can state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (eflag & EFLG_TXBO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) new_state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) can_id |= CAN_ERR_BUSOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else if (eflag & EFLG_TXEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) new_state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) data1 |= CAN_ERR_CRTL_TX_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else if (eflag & EFLG_RXEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) new_state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) data1 |= CAN_ERR_CRTL_RX_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) } else if (eflag & EFLG_TXWAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) new_state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) data1 |= CAN_ERR_CRTL_TX_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) } else if (eflag & EFLG_RXWAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) new_state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) data1 |= CAN_ERR_CRTL_RX_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) new_state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Update can state statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) switch (priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case CAN_STATE_ERROR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (new_state >= CAN_STATE_ERROR_WARNING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) new_state <= CAN_STATE_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) priv->can.can_stats.error_warning++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case CAN_STATE_ERROR_WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (new_state >= CAN_STATE_ERROR_PASSIVE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) new_state <= CAN_STATE_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) priv->can.can_stats.error_passive++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) priv->can.state = new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (intf & CANINTF_ERRIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Handle overflow counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (eflag & EFLG_RX0OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) net->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) net->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (eflag & EFLG_RX1OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) net->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) net->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) mcp251x_error_skb(net, can_id, data1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (priv->can.state == CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (priv->can.restart_ms == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) priv->can.can_stats.bus_off++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) can_bus_off(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (intf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (intf & CANINTF_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) net->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) net->stats.tx_bytes += priv->tx_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) can_led_event(net, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (priv->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) can_get_echo_skb(net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int mcp251x_open(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct mcp251x_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = open_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_err(&spi->dev, "unable to set initial baudrate!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mutex_lock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mcp251x_power_enable(priv->transceiver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!dev_fwnode(&spi->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) flags = IRQF_TRIGGER_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) flags | IRQF_ONESHOT, dev_name(&spi->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) goto out_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = mcp251x_hw_wake(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = mcp251x_setup(net, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = mcp251x_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) can_led_event(net, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) out_close:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) mcp251x_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) close_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mutex_unlock(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static const struct net_device_ops mcp251x_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .ndo_open = mcp251x_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .ndo_stop = mcp251x_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .ndo_start_xmit = mcp251x_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct of_device_id mcp251x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .compatible = "microchip,mcp2510",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .data = (void *)CAN_MCP251X_MCP2510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .compatible = "microchip,mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .data = (void *)CAN_MCP251X_MCP2515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .compatible = "microchip,mcp25625",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .data = (void *)CAN_MCP251X_MCP25625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) MODULE_DEVICE_TABLE(of, mcp251x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static const struct spi_device_id mcp251x_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .name = "mcp2510",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .name = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .name = "mcp25625",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int mcp251x_can_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) const void *match = device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct net_device *net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct mcp251x_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) clk = devm_clk_get_optional(&spi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) device_property_read_u32(&spi->dev, "clock-frequency", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (freq < 1000000 || freq > 25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Allocate can/net device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) net->netdev_ops = &mcp251x_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) net->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) priv->can.bittiming_const = &mcp251x_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) priv->can.do_set_mode = mcp251x_do_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) priv->can.clock.freq = freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) priv->model = (enum mcp251x_model)match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) priv->model = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) priv->net = net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) priv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) spi_set_drvdata(spi, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Configure the SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (mcp251x_is_2510(spi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = mcp251x_power_enable(priv->power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!priv->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) priv->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) mutex_init(&priv->mcp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!priv->spi_tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!priv->spi_rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SET_NETDEV_DEV(net, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Here is OK to not lock the MCP, no one knows about it yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = mcp251x_hw_probe(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) priv->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = register_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) devm_can_led_init(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ret = mcp251x_gpio_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) error_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) destroy_workqueue(priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) priv->wq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) mcp251x_power_enable(priv->power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) free_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static int mcp251x_can_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) unregister_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) mcp251x_power_enable(priv->power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) destroy_workqueue(priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) priv->wq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) free_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static int __maybe_unused mcp251x_can_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Note: at this point neither IST nor workqueues are running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * open/stop cannot be called anyway so locking is not needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (netif_running(net)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) netif_device_detach(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) mcp251x_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) mcp251x_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) priv->after_suspend = AFTER_SUSPEND_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) priv->after_suspend = AFTER_SUSPEND_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mcp251x_power_enable(priv->power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) priv->after_suspend |= AFTER_SUSPEND_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int __maybe_unused mcp251x_can_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct mcp251x_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (priv->after_suspend & AFTER_SUSPEND_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) mcp251x_power_enable(priv->power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (priv->after_suspend & AFTER_SUSPEND_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) mcp251x_power_enable(priv->transceiver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) queue_work(priv->wq, &priv->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) priv->after_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) enable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mcp251x_can_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static struct spi_driver mcp251x_can_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .of_match_table = mcp251x_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .pm = &mcp251x_can_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .id_table = mcp251x_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .probe = mcp251x_can_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .remove = mcp251x_can_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) module_spi_driver(mcp251x_can_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) "Christian Pellegrin <chripell@evolware.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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