^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(C) Timesys Corporation 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2009 Christian Pellegrin EVOL S.r.l.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2006 Arcom Control Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on CAN bus driver for the CCAN controller written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - Simon Kallweit, intefo AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright 2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/can/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI3110_MASTER_RESET 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI3110_READ_CTRL0 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI3110_READ_CTRL1 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HI3110_READ_STATF 0xE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI3110_WRITE_CTRL0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HI3110_WRITE_CTRL1 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HI3110_WRITE_INTE 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HI3110_WRITE_BTR0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HI3110_WRITE_BTR1 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI3110_READ_BTR0 0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HI3110_READ_BTR1 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HI3110_READ_INTF 0xDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI3110_READ_ERR 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI3110_READ_FIFO_WOTIME 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI3110_WRITE_FIFO 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI3110_READ_MESSTAT 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI3110_READ_REC 0xEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI3110_READ_TEC 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI3110_CTRL0_MODE_MASK (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI3110_CTRL0_NORMAL_MODE (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI3110_CTRL0_MONITOR_MODE (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI3110_CTRL0_SLEEP_MODE (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI3110_CTRL0_INIT_MODE (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI3110_CTRL1_TXEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HI3110_INT_RXTMP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HI3110_INT_RXFIFO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HI3110_INT_TXCPLT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI3110_INT_BUSERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HI3110_INT_MCHG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HI3110_INT_WAKEUP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HI3110_INT_F1MESS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HI3110_INT_F0MESS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HI3110_ERR_BUSOFF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI3110_ERR_TXERRP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HI3110_ERR_RXERRP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI3110_ERR_BITERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI3110_ERR_FRMERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI3110_ERR_CRCERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI3110_ERR_ACKERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HI3110_ERR_STUFERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI3110_ERR_PROTOCOL_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI3110_ERR_PASSIVE_MASK (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI3110_STAT_RXFMTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HI3110_STAT_BUSOFF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HI3110_STAT_ERRP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HI3110_STAT_ERRW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HI3110_STAT_TXMTY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HI3110_BTR0_SJW_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HI3110_BTR0_BRP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HI3110_BTR1_TSEG2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HI3110_BTR1_TSEG1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI3110_FIFO_WOTIME_TAG_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI3110_FIFO_WOTIME_ID_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI3110_FIFO_WOTIME_DLC_OFF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HI3110_FIFO_WOTIME_DAT_OFF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HI3110_FIFO_TAG_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HI3110_FIFO_ID_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HI3110_FIFO_STD_DLC_OFF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HI3110_FIFO_STD_DATA_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HI3110_FIFO_EXT_DLC_OFF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HI3110_FIFO_EXT_DATA_OFF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HI3110_CAN_MAX_DATA_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI3110_RX_BUF_LEN 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HI3110_TX_STD_BUF_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HI3110_TX_EXT_BUF_LEN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HI3110_CAN_FRAME_MAX_BITS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HI3110_TX_ECHO_SKB_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HI3110_OST_DELAY_MS (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DEVICE_NAME "hi3110"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct can_bittiming_const hi3110_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .tseg1_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .brp_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum hi3110_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CAN_HI3110_HI3110 = 0x3110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct hi3110_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct can_priv can;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct net_device *net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum hi3110_model model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mutex hi3110_lock; /* SPI device lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 *spi_tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 *spi_rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct work_struct tx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct work_struct restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int force_quit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int after_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HI3110_AFTER_SUSPEND_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HI3110_AFTER_SUSPEND_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HI3110_AFTER_SUSPEND_POWER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HI3110_AFTER_SUSPEND_RESTART 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int restart_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct regulator *power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct regulator *transceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void hi3110_clean(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (priv->tx_skb || priv->tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) net->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_kfree_skb(priv->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (priv->tx_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) can_free_echo_skb(priv->net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Note about handling of error return of hi3110_spi_trans: accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * registers via SPI is not really different conceptually than using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * normal I/O assembler instructions, although it's much more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * complicated from a practical POV. So it's not advisable to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * check the return value of this function. Imagine that every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * error();", it would be a great mess (well there are some situation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * when exception handling C++ like could be useful after all). So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * just check that transfers are OK at the beginning of our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * conversation with the chip and to avoid doing really nasty things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * (like injecting bogus packets in the network stack).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int hi3110_spi_trans(struct spi_device *spi, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct spi_transfer t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .tx_buf = priv->spi_tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .rx_buf = priv->spi_rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .cs_change = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int hi3110_cmd(struct spi_device *spi, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) priv->spi_tx_buf[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return hi3110_spi_trans(spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static u8 hi3110_read(struct spi_device *spi, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) priv->spi_tx_buf[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) hi3110_spi_trans(spi, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val = priv->spi_rx_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) priv->spi_tx_buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) priv->spi_tx_buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hi3110_spi_trans(spi, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) memcpy(priv->spi_tx_buf + 1, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) hi3110_spi_trans(spi, len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 buf[HI3110_TX_EXT_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) buf[HI3110_FIFO_TAG_OFF] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (frame->can_id & CAN_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Extended frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) buf[HI3110_FIFO_ID_OFF + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) HI3110_EFF_FLAGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) buf[HI3110_FIFO_ID_OFF + 2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (frame->can_id & CAN_EFF_MASK) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) buf[HI3110_FIFO_ID_OFF + 3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ((frame->can_id & CAN_EFF_MASK) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) frame->data, frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Standard frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) buf[HI3110_FIFO_ID_OFF + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ((frame->can_id & CAN_SFF_MASK) << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) frame->data, frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void hi3110_hw_rx(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 buf[HI3110_RX_BUF_LEN - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) skb = alloc_can_skb(priv->net, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) priv->net->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hi3110_hw_rx_frame(spi, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* IDE is recessive (1), indicating extended 29-bit frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) frame->can_id = CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) frame->can_id |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* IDE is dominant (0), frame indicating standard 11-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) frame->can_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) frame->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) priv->net->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) priv->net->stats.rx_bytes += frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) can_led_event(priv->net, CAN_LED_EVENT_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void hi3110_hw_sleep(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (priv->tx_skb || priv->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(&spi->dev, "hard_xmit called while tx busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (can_dropped_invalid_skb(net, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) netif_stop_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) queue_work(priv->wq, &priv->tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hi3110_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* We have to delay work since SPI I/O may sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) priv->restart_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (priv->can.restart_ms == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) queue_work(priv->wq, &priv->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int hi3110_get_berr_counter(const struct net_device *net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int hi3110_set_normal_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Enable TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) reg = HI3110_CTRL0_LOOPBACK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) reg = HI3110_CTRL0_MONITOR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) reg = HI3110_CTRL0_NORMAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Wait for the device to enter the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mdelay(HI3110_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) reg = hi3110_read(spi, HI3110_READ_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int hi3110_do_set_bittiming(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) hi3110_write(spi, HI3110_WRITE_BTR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hi3110_write(spi, HI3110_WRITE_BTR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (priv->can.ctrlmode &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CAN_CTRLMODE_3_SAMPLES ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ((bt->phase_seg1 + bt->prop_seg - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) << HI3110_BTR1_TSEG1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hi3110_read(spi, HI3110_READ_BTR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hi3110_read(spi, HI3110_READ_BTR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int hi3110_setup(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hi3110_do_set_bittiming(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int hi3110_hw_reset(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Wait for oscillator startup timer after power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mdelay(HI3110_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Wait for oscillator startup timer after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mdelay(HI3110_OST_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) reg = hi3110_read(spi, HI3110_READ_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* As per the datasheet it appears the error flags are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * not cleared on reset. Explicitly clear them by performing a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) hi3110_read(spi, HI3110_READ_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int hi3110_hw_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 statf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hi3110_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Confirm correct operation by checking against reset values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * in datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) statf = hi3110_read(spi, HI3110_READ_STATF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_dbg(&spi->dev, "statf: %02X\n", statf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (statf != 0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int hi3110_power_enable(struct regulator *reg, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (IS_ERR_OR_NULL(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return regulator_enable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return regulator_disable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int hi3110_stop(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) close_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) destroy_workqueue(priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) priv->wq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Disable transmit, interrupts and clear flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hi3110_read(spi, HI3110_READ_INTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hi3110_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hi3110_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) can_led_event(net, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void hi3110_tx_work_handler(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tx_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (priv->tx_skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (priv->can.state == CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hi3110_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) frame = (struct can_frame *)priv->tx_skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hi3110_hw_tx(spi, frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) priv->tx_len = 1 + frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) can_put_echo_skb(priv->tx_skb, net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void hi3110_restart_work_handler(struct work_struct *ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (priv->after_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) hi3110_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) hi3110_setup(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hi3110_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) netif_device_attach(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hi3110_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) hi3110_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) priv->after_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (priv->restart_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) priv->restart_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) hi3110_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) hi3110_setup(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hi3110_clean(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) hi3110_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct hi3110_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) while (!priv->force_quit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) enum can_state new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 intf, eflag, statf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) while (!(HI3110_STAT_RXFMTY &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (statf = hi3110_read(spi, HI3110_READ_STATF)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hi3110_hw_rx(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) intf = hi3110_read(spi, HI3110_READ_INTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) eflag = hi3110_read(spi, HI3110_READ_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Update can state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (eflag & HI3110_ERR_BUSOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) new_state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else if (eflag & HI3110_ERR_PASSIVE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) new_state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) else if (statf & HI3110_STAT_ERRW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) new_state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) new_state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (new_state != priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) enum can_state rx_state, tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u8 rxerr, txerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) skb = alloc_can_err_skb(net, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) txerr = hi3110_read(spi, HI3110_READ_TEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rxerr = hi3110_read(spi, HI3110_READ_REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) cf->data[6] = txerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) cf->data[7] = rxerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tx_state = txerr >= rxerr ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) rx_state = txerr <= rxerr ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) can_change_state(net, cf, tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (new_state == CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) can_bus_off(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (priv->can.restart_ms == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Update bus errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if ((intf & HI3110_INT_BUSERR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Check for protocol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (eflag & HI3110_ERR_PROTOCOL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) skb = alloc_can_err_skb(net, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) priv->net->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (eflag & HI3110_ERR_BITERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) else if (eflag & HI3110_ERR_FRMERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else if (eflag & HI3110_ERR_STUFERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else if (eflag & HI3110_ERR_CRCERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else if (eflag & HI3110_ERR_ACKERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) netdev_dbg(priv->net, "Bus Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (priv->tx_len && statf & HI3110_STAT_TXMTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) net->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) net->stats.tx_bytes += priv->tx_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) can_led_event(net, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (priv->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) can_get_echo_skb(net, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (intf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int hi3110_open(struct net_device *net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct hi3110_priv *priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = open_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mutex_lock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) hi3110_power_enable(priv->transceiver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->tx_skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) priv->tx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) flags, DEVICE_NAME, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto out_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!priv->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = hi3110_hw_reset(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto out_free_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = hi3110_setup(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto out_free_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret = hi3110_set_normal_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto out_free_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) can_led_event(net, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) netif_wake_queue(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) out_free_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) destroy_workqueue(priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) free_irq(spi->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) out_close:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) hi3110_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) close_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mutex_unlock(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct net_device_ops hi3110_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .ndo_open = hi3110_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .ndo_stop = hi3110_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .ndo_start_xmit = hi3110_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct of_device_id hi3110_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .compatible = "holt,hi3110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .data = (void *)CAN_HI3110_HI3110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) MODULE_DEVICE_TABLE(of, hi3110_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct spi_device_id hi3110_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .name = "hi3110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MODULE_DEVICE_TABLE(spi, hi3110_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int hi3110_can_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) const struct of_device_id *of_id = of_match_device(hi3110_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct net_device *net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct hi3110_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int freq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk = devm_clk_get(&spi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(&spi->dev, "no CAN clock source defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (freq > 40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Allocate can/net device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) net->netdev_ops = &hi3110_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) net->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) priv = netdev_priv(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->can.bittiming_const = &hi3110_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) priv->can.do_set_mode = hi3110_do_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) priv->can.do_get_berr_counter = hi3110_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) priv->can.clock.freq = freq / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) CAN_CTRLMODE_LOOPBACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) CAN_CTRLMODE_LISTENONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) CAN_CTRLMODE_BERR_REPORTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) priv->model = (enum hi3110_model)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv->model = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) priv->net = net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) priv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) spi_set_drvdata(spi, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Configure the SPI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = hi3110_power_enable(priv->power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) priv->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mutex_init(&priv->hi3110_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!priv->spi_tx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!priv->spi_rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SET_NETDEV_DEV(net, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = hi3110_hw_probe(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) priv->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = register_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) goto error_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) devm_can_led_init(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) netdev_info(net, "%x successfully initialized.\n", priv->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) error_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) hi3110_power_enable(priv->power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) free_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static int hi3110_can_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unregister_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) hi3110_power_enable(priv->power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (!IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) free_candev(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int __maybe_unused hi3110_can_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct net_device *net = priv->net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) priv->force_quit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Note: at this point neither IST nor workqueues are running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * open/stop cannot be called anyway so locking is not needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (netif_running(net)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) netif_device_detach(net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) hi3110_hw_sleep(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) hi3110_power_enable(priv->transceiver, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!IS_ERR_OR_NULL(priv->power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) regulator_disable(priv->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int __maybe_unused hi3110_can_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct hi3110_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) hi3110_power_enable(priv->power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) hi3110_power_enable(priv->transceiver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) queue_work(priv->wq, &priv->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) priv->after_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) priv->force_quit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) enable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static struct spi_driver hi3110_can_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .of_match_table = hi3110_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .pm = &hi3110_can_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .id_table = hi3110_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .probe = hi3110_can_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .remove = hi3110_can_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) module_spi_driver(hi3110_can_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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