^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * softing common interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * by Kurt Van Dijck, 2008-2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/can.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "softing_platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct softing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct softing_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct can_priv can; /* must be the first member! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct softing *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* variables which hold the circular buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int echo_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int echo_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct can_bittiming_const btr_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) uint8_t output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) uint16_t chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define netdev2softing(netdev) ((struct softing_priv *)netdev_priv(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct softing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct softing_platform_data *pdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct net_device *net[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spinlock_t spin; /* protect this structure & DPRAM access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ktime_t ts_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ktime_t ts_overflow; /* timestamp overflow value, in ktime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* indication of firmware status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* protection of the 'up' variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int svc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int dpram_position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int last_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * keep the bus that last tx'd a message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * in order to let every netdev queue resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __iomem uint8_t *dpram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long dpram_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long dpram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uint16_t fw_version, hw_version, license, serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) uint16_t chip[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int freq; /* remote cpu's operating frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int softing_default_output(struct net_device *netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ktime_t softing_raw2ktime(struct softing *card, u32 raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int softing_chip_poweron(struct softing *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int softing_bootloader_command(struct softing *card, int16_t cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Load firmware after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int softing_load_fw(const char *file, struct softing *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __iomem uint8_t *virt, unsigned int size, int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Load final application firmware after bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int softing_load_app_fw(const char *file, struct softing *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * enable or disable irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * only called with fw.lock locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int softing_enable_irq(struct softing *card, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* start/stop 1 bus on card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int softing_startstop(struct net_device *netdev, int up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* netif_rx() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int softing_netdev_rx(struct net_device *netdev, const struct can_frame *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ktime_t ktime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SOFTING DPRAM mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DPRAM_RX 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DPRAM_RX_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DPRAM_RX_CNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DPRAM_RX_RD 0x0201 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DPRAM_RX_WR 0x0205 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DPRAM_RX_LOST 0x0207 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DPRAM_FCT_PARAM 0x0300 /* int16_t [20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DPRAM_FCT_RESULT 0x0328 /* int16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DPRAM_FCT_HOST 0x032b /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DPRAM_INFO_BUSSTATE 0x0331 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DPRAM_INFO_BUSSTATE2 0x0335 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DPRAM_INFO_ERRSTATE 0x0339 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DPRAM_INFO_ERRSTATE2 0x033d /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DPRAM_RESET 0x0341 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DPRAM_CLR_RECV_FIFO 0x0345 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DPRAM_RESET_TIME 0x034d /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DPRAM_TIME 0x0350 /* uint64_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DPRAM_WR_START 0x0358 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DPRAM_WR_END 0x0359 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DPRAM_RESET_RX_FIFO 0x0361 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DPRAM_RESET_TX_FIFO 0x0364 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DPRAM_READ_FIFO_LEVEL 0x0365 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DPRAM_RX_FIFO_LEVEL 0x0366 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DPRAM_TX_FIFO_LEVEL 0x0366 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DPRAM_TX 0x0400 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DPRAM_TX_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DPRAM_TX_CNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DPRAM_TX_RD 0x0601 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DPRAM_TX_WR 0x0605 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DPRAM_COMMAND 0x07e0 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DPRAM_RECEIPT 0x07f0 /* uint16_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DPRAM_IRQ_TOHOST 0x07fe /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DPRAM_IRQ_TOCARD 0x07ff /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DPRAM_V2_RESET 0x0e00 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DPRAM_V2_IRQ_TOHOST 0x0e02 /* uint8_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TXMAX (DPRAM_TX_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* DPRAM return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RES_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RES_OK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RES_NOK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RES_UNKNOWN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* DPRAM flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMD_TX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMD_ACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CMD_XTD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CMD_RTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CMD_ERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CMD_BUS2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* returned fifo entry bus state masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SF_MASK_BUSOFF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SF_MASK_EPASSIVE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* bus states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define STATE_BUSOFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define STATE_EPASSIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define STATE_EACTIVE 0
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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