Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * sja1000.h -  Philips SJA1000 network device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * 38106 Braunschweig, GERMANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *    notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *    documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * 3. Neither the name of Volkswagen nor the names of its contributors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *    may be used to endorse or promote products derived from this software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *    without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Alternatively, provided that this notice is retained in full, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * software may be distributed under the terms of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Public License ("GPL") version 2, in which case the provisions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * GPL apply INSTEAD OF those given above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * The provided data structures and external interfaces from this code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * are not restricted to be used by modules with a GPL compatible license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifndef SJA1000_DEV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SJA1000_DEV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <linux/can/platform/sja1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SJA1000_ECHO_SKB_MAX	1 /* the SJA1000 has one TX buffer object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SJA1000_MAX_IRQ 20	/* max. number of interrupts handled in ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SJA1000_MOD		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SJA1000_CMR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SJA1000_SR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SJA1000_IR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SJA1000_IER		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SJA1000_ALC		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SJA1000_ECC		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SJA1000_EWL		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SJA1000_RXERR		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SJA1000_TXERR		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SJA1000_ACCC0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SJA1000_ACCC1		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SJA1000_ACCC2		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SJA1000_ACCC3		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SJA1000_ACCM0		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SJA1000_ACCM1		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SJA1000_ACCM2		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SJA1000_ACCM3		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SJA1000_RMC		0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SJA1000_RBSA		0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* Common registers - manual section 6.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SJA1000_BTR0		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SJA1000_BTR1		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SJA1000_OCR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SJA1000_CDR		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SJA1000_FI		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SJA1000_SFF_BUF		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SJA1000_EFF_BUF		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SJA1000_FI_FF		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SJA1000_FI_RTR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SJA1000_ID1		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SJA1000_ID2		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SJA1000_ID3		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SJA1000_ID4		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SJA1000_CAN_RAM		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MOD_RM		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MOD_LOM		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MOD_STM		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MOD_AFM		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MOD_SM		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMD_SRR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMD_CDO		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CMD_RRB		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMD_AT		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMD_TR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IRQ_BEI		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IRQ_ALI		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IRQ_EPI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IRQ_WUI		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IRQ_DOI		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IRQ_EI		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IRQ_TI		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IRQ_RI		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IRQ_ALL		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IRQ_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* status register content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SR_BS		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SR_ES		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SR_TS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SR_RS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SR_TCS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SR_TBS		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SR_DOS		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SR_RBS		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SR_CRIT (SR_BS|SR_ES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* ECC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ECC_SEG		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ECC_DIR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ECC_ERR		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ECC_BIT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ECC_FORM	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ECC_STUFF	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ECC_MASK	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * Flags for sja1000priv.flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SJA1000_CUSTOM_IRQ_HANDLER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * SJA1000 private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct sja1000_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct can_priv can;	/* must be the first member */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct sk_buff *echo_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* the lower-layer is responsible for appropriate locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u8 (*read_reg) (const struct sja1000_priv *priv, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	void (*pre_irq) (const struct sja1000_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	void (*post_irq) (const struct sja1000_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	void *priv;		/* for board-specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	void __iomem *reg_base;	 /* ioremap'ed address to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned long irq_flags; /* for request_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	spinlock_t cmdreg_lock;  /* lock for concurrent cmd register writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u16 flags;		/* custom mode flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 ocr;			/* output control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 cdr;			/* clock divider register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct net_device *alloc_sja1000dev(int sizeof_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void free_sja1000dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int register_sja1000dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void unregister_sja1000dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irqreturn_t sja1000_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif /* SJA1000_DEV_H */