^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999 - 2010 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/can.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCH_CTRL_CCE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCH_CMASK_RX_TX_SET 0x00f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCH_CMASK_RX_TX_GET 0x0073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCH_CMASK_ALL 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCH_CMASK_NEWDAT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCH_CMASK_CLRINTPND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCH_CMASK_CTRL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCH_CMASK_ARB BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCH_CMASK_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCH_CMASK_RDWR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCH_IF_MCONT_NEWDAT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCH_IF_MCONT_MSGLOST BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCH_IF_MCONT_INTPND BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCH_IF_MCONT_UMASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCH_IF_MCONT_TXIE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCH_IF_MCONT_RXIE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCH_IF_MCONT_RMTEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCH_IF_MCONT_TXRQXT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCH_IF_MCONT_EOB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCH_ID2_DIR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCH_ID2_XTD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCH_ID_MSGVAL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCH_IF_CREQ_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCH_STATUS_INT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCH_RP 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCH_REC 0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCH_TEC 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCH_TX_OK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCH_RX_OK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCH_EPASSIV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCH_EWARN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCH_BUS_OFF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* bit position of certain controller bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCH_BIT_BRP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCH_BIT_SJW_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCH_BIT_TSEG1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCH_BIT_TSEG2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCH_BIT_BRPE_BRPE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCH_MSK_BITT_BRP 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCH_MSK_BRPE_BRPE 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCH_COUNTER_LIMIT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCH_CAN_CLK 50000000 /* 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Define the number of message object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * PCH CAN communications are done via Message RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The Message RAM consists of 32 message objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCH_RX_OBJ_NUM 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCH_TX_OBJ_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCH_RX_OBJ_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCH_FIFO_THRESH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* TxRqst2 show status of MsgObjNo.17~32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (PCH_RX_OBJ_END - 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum pch_ifreg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PCH_RX_IFREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PCH_TX_IFREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum pch_can_err {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PCH_STUF_ERR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PCH_FORM_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PCH_ACK_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PCH_BIT1_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PCH_BIT0_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PCH_CRC_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PCH_LEC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum pch_can_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PCH_CAN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PCH_CAN_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PCH_CAN_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PCH_CAN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PCH_CAN_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PCH_CAN_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pch_can_if_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 creq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 cmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 id1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 mcont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 rsv[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pch_can_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 cont;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 errc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 bitt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 brpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 reserve1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 treq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 treq2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 reserve2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 reserve3[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 canipend1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 canipend2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 reserve4[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 canmval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 canmval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 reserve5[37];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 srst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pch_can_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct can_priv can;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 tx_enable[PCH_TX_OBJ_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 rx_enable[PCH_TX_OBJ_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 rx_link[PCH_TX_OBJ_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 int_enables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pch_can_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int tx_obj; /* Point next Tx Obj index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int use_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct can_bittiming_const pch_can_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .tseg1_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .tseg2_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .brp_max = 1024, /* 6bit + extended 4bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct pci_device_id pch_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) iowrite32(ioread32(addr) | mask, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iowrite32(ioread32(addr) & ~mask, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void pch_can_set_run_mode(struct pch_can_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum pch_can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case PCH_CAN_RUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case PCH_CAN_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void pch_can_set_optmode(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 reg_val = ioread32(&priv->regs->opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg_val |= PCH_OPT_SILENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg_val |= PCH_OPT_LBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) iowrite32(reg_val, &priv->regs->opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int counter = PCH_COUNTER_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 ifx_creq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) iowrite32(num, creq_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) while (counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!ifx_creq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) counter--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void pch_can_set_int_enables(struct pch_can_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum pch_can_mode interrupt_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (interrupt_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case PCH_CAN_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case PCH_CAN_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case PCH_CAN_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) netdev_err(priv->ndev, "Invalid interrupt number.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int set, enum pch_ifreg dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 ie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ie = PCH_IF_MCONT_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ie = PCH_IF_MCONT_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) &priv->regs->ifregs[dir].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Setting the MsgVal and RxIE/TxIE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Clearing the MsgVal and RxIE/TxIE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Traversing to obtain the object configured as receivers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Traversing to obtain the object configured as transmit object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static u32 pch_can_int_pending(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ioread32(&priv->regs->intr) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int i; /* Msg Obj ID (1~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iowrite32(0x0, &priv->regs->ifregs[0].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) iowrite32(0x0, &priv->regs->ifregs[0].id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iowrite32(0x0, &priv->regs->ifregs[0].mcont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PCH_CMASK_ARB | PCH_CMASK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) iowrite32(0x0, &priv->regs->ifregs[0].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) iowrite32(0x0, &priv->regs->ifregs[0].id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pch_can_bit_set(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PCH_IF_MCONT_UMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (i == PCH_RX_OBJ_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pch_can_bit_set(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PCH_IF_MCONT_EOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PCH_IF_MCONT_EOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) iowrite32(0, &priv->regs->ifregs[0].mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x1fff | PCH_MASK2_MDIR_MXTD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Setting CMASK for writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Resetting DIR bit for reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) iowrite32(0x0, &priv->regs->ifregs[1].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Setting EOB bit for transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &priv->regs->ifregs[1].mcont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) iowrite32(0, &priv->regs->ifregs[1].mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Setting CMASK for writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void pch_can_init(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Stopping the Can device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pch_can_set_run_mode(priv, PCH_CAN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Clearing all the message object buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pch_can_clear_if_buffers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Configuring the respective message object as either rx/tx object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pch_can_config_rx_tx_buffers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Enabling the interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pch_can_set_int_enables(priv, PCH_CAN_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void pch_can_release(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Stooping the CAN device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pch_can_set_run_mode(priv, PCH_CAN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Disabling the interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pch_can_set_int_enables(priv, PCH_CAN_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Disabling all the receive object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pch_can_set_rx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Disabling all the transmit object. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pch_can_set_tx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* This function clears interrupt(s) from the CAN device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Clear interrupt for transmit object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Setting CMASK for clearing the reception interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Clearing the Dir bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Clearing NewDat & IntPnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Setting CMASK for clearing interrupts for frame transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &priv->regs->ifregs[1].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Resetting the ID registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pch_can_bit_set(&priv->regs->ifregs[1].id2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PCH_ID2_DIR | (0x7ff << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) iowrite32(0x0, &priv->regs->ifregs[1].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Clearing NewDat, TxRqst & IntPnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PCH_IF_MCONT_TXRQXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void pch_can_reset(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* write to sw reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) iowrite32(1, &priv->regs->srst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iowrite32(0, &priv->regs->srst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void pch_can_error(struct net_device *ndev, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 errc, lec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct net_device_stats *stats = &(priv->ndev->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum can_state state = priv->can.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) skb = alloc_can_err_skb(ndev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (status & PCH_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pch_can_set_tx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pch_can_set_rx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cf->can_id |= CAN_ERR_BUSOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) priv->can.can_stats.bus_off++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) can_bus_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) errc = ioread32(&priv->regs->errc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Warning interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (status & PCH_EWARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) priv->can.can_stats.error_warning++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (((errc & PCH_REC) >> 8) > 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if ((errc & PCH_TEC) > 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) netdev_dbg(ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "%s -> Error Counter is more than 96.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Error passive interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (status & PCH_EPASSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) priv->can.can_stats.error_passive++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (errc & PCH_RP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if ((errc & PCH_TEC) > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) netdev_dbg(ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) lec = status & PCH_LEC_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) switch (lec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case PCH_STUF_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case PCH_FORM_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case PCH_ACK_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cf->can_id |= CAN_ERR_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case PCH_BIT1_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case PCH_BIT0_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case PCH_CRC_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case PCH_LEC_ALL: /* Written by CPU. No error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cf->data[6] = errc & PCH_TEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) cf->data[7] = (errc & PCH_REC) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) priv->can.state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct net_device *ndev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!pch_can_int_pending(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pch_can_set_int_enables(priv, PCH_CAN_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (obj_id < PCH_FIFO_THRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Clearing the Dir bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Clearing NewDat & IntPnd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PCH_IF_MCONT_INTPND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else if (obj_id > PCH_FIFO_THRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pch_can_int_clr(priv, obj_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) } else if (obj_id == PCH_FIFO_THRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pch_can_int_clr(priv, cnt + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct net_device_stats *stats = &(priv->ndev->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PCH_IF_MCONT_MSGLOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) skb = alloc_can_err_skb(ndev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) stats->rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) canid_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int rcv_pkts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct net_device_stats *stats = &(priv->ndev->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u16 data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Reading the message object from the Message RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Reading the MCONT register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) reg = ioread32(&priv->regs->ifregs[0].mcont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (reg & PCH_IF_MCONT_EOB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* If MsgLost bit set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (reg & PCH_IF_MCONT_MSGLOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pch_can_rx_msg_lost(ndev, obj_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rcv_pkts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) quota--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) obj_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) obj_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) skb = alloc_can_skb(priv->ndev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) netdev_err(ndev, "alloc_can_skb Failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return rcv_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Get Received data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) id2 = ioread32(&priv->regs->ifregs[0].id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (id2 & PCH_ID2_XTD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) id |= (((id2) & 0x1fff) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) cf->can_id = id | CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) id = (id2 >> 2) & CAN_SFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cf->can_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (id2 & PCH_ID2_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cf->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ifregs[0].mcont)) & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) for (i = 0; i < cf->can_dlc; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cf->data[i] = data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) cf->data[i + 1] = data_reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) rcv_pkts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) quota--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pch_fifo_thresh(priv, obj_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) obj_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) } while (quota > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return rcv_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct net_device_stats *stats = &(priv->ndev->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) &priv->regs->ifregs[1].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PCH_IF_MCONT_DLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) stats->tx_bytes += dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (int_stat == PCH_TX_OBJ_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int pch_can_poll(struct napi_struct *napi, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct net_device *ndev = napi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 reg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int quota_save = quota;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int_stat = pch_can_int_pending(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!int_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (int_stat == PCH_STATUS_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) reg_stat = ioread32(&priv->regs->stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pch_can_error(ndev, reg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) quota--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pch_can_bit_clear(&priv->regs->stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) reg_stat & (PCH_TX_OK | PCH_RX_OK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int_stat = pch_can_int_pending(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (quota == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) quota -= pch_can_rx_normal(ndev, int_stat, quota);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else if ((int_stat >= PCH_TX_OBJ_START) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (int_stat <= PCH_TX_OBJ_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Handle transmission interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pch_can_tx_complete(ndev, int_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) napi_complete(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pch_can_set_int_enables(priv, PCH_CAN_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return quota_save - quota;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int pch_set_bittiming(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) const struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 canbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 bepe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Setting the CCE bit for accessing the Can Timing register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) iowrite32(canbit, &priv->regs->bitt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) iowrite32(bepe, &priv->regs->brpe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void pch_can_start(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (priv->can.state != CAN_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pch_can_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pch_set_bittiming(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pch_can_set_optmode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pch_can_set_tx_all(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pch_can_set_rx_all(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Setting the CAN to run mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pch_can_set_run_mode(priv, PCH_CAN_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pch_can_start(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int pch_can_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Registering the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ndev->name, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) netdev_err(ndev, "request_irq failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto req_irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Open common can device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) retval = open_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) netdev_err(ndev, "open_candev() failed %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) goto err_open_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pch_can_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pch_can_start(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) err_open_candev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) free_irq(priv->dev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) req_irq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pch_can_release(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int pch_close(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) pch_can_release(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) free_irq(priv->dev->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) close_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct can_frame *cf = (struct can_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int tx_obj_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (can_dropped_invalid_skb(ndev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tx_obj_no = priv->tx_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (priv->tx_obj == PCH_TX_OBJ_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) priv->tx_obj = PCH_TX_OBJ_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) priv->tx_obj++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Setting the CMASK register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* If ID extended is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (cf->can_id & CAN_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) iowrite32(0, &priv->regs->ifregs[1].id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) id2 = (cf->can_id & CAN_SFF_MASK) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) id2 |= PCH_ID_MSGVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* If remote frame has to be transmitted.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!(cf->can_id & CAN_RTR_FLAG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) id2 |= PCH_ID2_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) iowrite32(id2, &priv->regs->ifregs[1].id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Copy data to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) for (i = 0; i < cf->can_dlc; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &priv->regs->ifregs[1].data[i / 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Set the size of the data. Update if2_mcont */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct net_device_ops pch_can_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ndo_open = pch_can_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .ndo_stop = pch_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .ndo_start_xmit = pch_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static void pch_can_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct net_device *ndev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct pch_can_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unregister_candev(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (priv->use_msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pci_disable_msi(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pch_can_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pci_iounmap(pdev, priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) free_candev(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void __maybe_unused pch_can_set_int_custom(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Clearing the IE, SIE and EIE bits of Can control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Appropriately setting them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pch_can_bit_set(&priv->regs->cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* This function retrieves interrupt enabled for the CAN device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static u32 __maybe_unused pch_can_get_int_enables(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Obtaining the status of IE, SIE and EIE interrupt bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static u32 __maybe_unused pch_can_get_rxtx_ir(struct pch_can_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 buff_num, enum pch_ifreg dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 ie, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ie = PCH_IF_MCONT_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ie = PCH_IF_MCONT_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static void __maybe_unused pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u32 buffer_num, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PCH_IF_MCONT_EOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static u32 __maybe_unused pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 buffer_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int __maybe_unused pch_can_get_buffer_status(struct pch_can_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return (ioread32(&priv->regs->treq1) & 0xffff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) (ioread32(&priv->regs->treq2) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int __maybe_unused pch_can_suspend(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 buf_stat; /* Variable for reading the transmit buffer status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int counter = PCH_COUNTER_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct pch_can_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Stop the CAN controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pch_can_set_run_mode(priv, PCH_CAN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Indicate that we are aboutto/in suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Waiting for all transmission to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) while (counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) buf_stat = pch_can_get_buffer_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!buf_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) counter--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_err(dev_d, "%s -> Transmission time out.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Save interrupt configuration and then disable them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) priv->int_enables = pch_can_get_int_enables(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Save Tx buffer enable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PCH_TX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* Disable all Transmit buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pch_can_set_tx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Save Rx buffer enable state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PCH_RX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Disable all Receive buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pch_can_set_rx_all(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int __maybe_unused pch_can_resume(struct device *dev_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct net_device *dev = dev_get_drvdata(dev_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct pch_can_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* Disabling all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Setting the CAN device in Stop Mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) pch_can_set_run_mode(priv, PCH_CAN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Configuring the transmit and receive buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pch_can_config_rx_tx_buffers(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Restore the CAN state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pch_set_bittiming(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Listen/Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) pch_can_set_optmode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* Enabling the transmit buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Configuring the receive buffer and enabling them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Restore buffer link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* Restore buffer enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Enable CAN Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pch_can_set_int_custom(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Restore Run Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pch_can_set_run_mode(priv, PCH_CAN_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static int pch_can_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct pch_can_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 errc = ioread32(&priv->regs->errc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) bec->txerr = errc & PCH_TEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) bec->rxerr = (errc & PCH_REC) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int pch_can_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct pch_can_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) goto probe_exit_endev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) rc = pci_request_regions(pdev, KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) goto probe_exit_pcireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) addr = pci_iomap(pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev_err(&pdev->dev, "Failed pci_iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) goto probe_exit_ipmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(&pdev->dev, "Failed alloc_candev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) goto probe_exit_alloc_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) priv->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) priv->regs = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) priv->dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) priv->can.bittiming_const = &pch_can_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) priv->can.do_set_mode = pch_can_do_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) priv->can.do_get_berr_counter = pch_can_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) CAN_CTRLMODE_LOOPBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ndev->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ndev->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pci_set_drvdata(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ndev->netdev_ops = &pch_can_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) rc = pci_enable_msi(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) netdev_err(ndev, "PCH CAN opened without MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) priv->use_msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) netdev_err(ndev, "PCH CAN opened with MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) priv->use_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rc = register_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto probe_exit_reg_candev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) probe_exit_reg_candev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (priv->use_msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pci_disable_msi(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) free_candev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) probe_exit_alloc_candev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) pci_iounmap(pdev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) probe_exit_ipmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) probe_exit_pcireq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) probe_exit_endev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static SIMPLE_DEV_PM_OPS(pch_can_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pch_can_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pch_can_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static struct pci_driver pch_can_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .name = "pch_can",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .id_table = pch_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .probe = pch_can_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .remove = pch_can_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .driver.pm = &pch_can_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) module_pci_driver(pch_can_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MODULE_VERSION("0.94");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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