^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CAN bus driver for the alone generic (as possible as) MSCAN controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Varma Electronics Oy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/if_arp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mscan.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct can_bittiming_const mscan_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "mscan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .tseg1_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .brp_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mscan_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 canrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 cantier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static enum can_state state_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CAN_STATE_ERROR_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CAN_STATE_ERROR_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CAN_STATE_ERROR_PASSIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CAN_STATE_BUS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int mscan_set_mode(struct net_device *dev, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 canctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (mode != MSCAN_NORMAL_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (priv->tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Abort transfers before going to sleep */#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) out_8(®s->cantarq, priv->tx_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Suppress TX done interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) out_8(®s->cantier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) canctl1 = in_8(®s->canctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) setbits8(®s->canctl0, MSCAN_SLPRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (in_8(®s->canctl1) & MSCAN_SLPAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The mscan controller will fail to enter sleep mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * while there are irregular activities on bus, like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * somebody keeps retransmitting. This behavior is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * undocumented and seems to differ between mscan built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * in mpc5200b and mpc5200. We proceed in that case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * since otherwise the slprq will be kept set and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * controller will get stuck. NOTE: INITRQ or CSWAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * will abort all active transmit actions, if still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * any, at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (i >= MSCAN_SET_MODE_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) netdev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "device failed to enter sleep mode. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "We proceed anyhow.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) priv->can.state = CAN_STATE_SLEEPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) setbits8(®s->canctl0, MSCAN_INITRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (in_8(®s->canctl1) & MSCAN_INITAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (i >= MSCAN_SET_MODE_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (mode & MSCAN_CSWAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) setbits8(®s->canctl0, MSCAN_CSWAI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) canctl1 = in_8(®s->canctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) canctl1 = in_8(®s->canctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (i >= MSCAN_SET_MODE_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int mscan_start(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 canrflg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) out_8(®s->canrier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) INIT_LIST_HEAD(&priv->tx_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) priv->prev_buf_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) priv->cur_pri = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) priv->tx_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) priv->shadow_canrier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) priv->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (priv->type == MSCAN_TYPE_MPC5121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Clear pending bus-off condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (in_8(®s->canmisc) & MSCAN_BOHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) out_8(®s->canmisc, MSCAN_BOHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) canrflg = in_8(®s->canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MSCAN_STATE_TX(canrflg))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) out_8(®s->cantier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Enable receive interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int mscan_restart(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (priv->type == MSCAN_TYPE_MPC5121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) WARN(!(in_8(®s->canmisc) & MSCAN_BOHOLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "bus-off state expected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) out_8(®s->canmisc, MSCAN_BOHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Re-enable receive interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (priv->can.state <= CAN_STATE_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mscan_set_mode(dev, MSCAN_INIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return mscan_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct can_frame *frame = (struct can_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i, rtr, buf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (can_dropped_invalid_skb(dev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) out_8(®s->cantier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) i = ~priv->tx_active & MSCAN_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) buf_id = ffs(i) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (hweight8(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) netdev_err(dev, "Tx Ring full when queue awake!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * if buf_id < 3, then current frame will be send out of order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * since buffer with lower id have higher priority (hell..)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (buf_id < priv->prev_buf_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) priv->cur_pri++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (priv->cur_pri == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) set_bit(F_TX_WAIT_ALL, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) set_bit(F_TX_PROGRESS, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) priv->prev_buf_id = buf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) out_8(®s->cantbsel, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rtr = frame->can_id & CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* RTR is always the lowest bit of interest, then IDs follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (frame->can_id & CAN_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) can_id = (frame->can_id & CAN_EFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) << (MSCAN_EFF_RTR_SHIFT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (rtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) out_be16(®s->tx.idr3_2, can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) can_id >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* EFF_FLAGS are between the IDs :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) | MSCAN_EFF_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) can_id = (frame->can_id & CAN_SFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) << (MSCAN_SFF_RTR_SHIFT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (rtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) out_be16(®s->tx.idr1_0, can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!rtr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void __iomem *data = ®s->tx.dsr1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 *payload = (u16 *)frame->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (i = 0; i < frame->can_dlc / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out_be16(data, *payload++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) data += 2 + _MSCAN_RESERVED_DSR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* write remaining byte if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (frame->can_dlc & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out_8(data, frame->data[frame->can_dlc - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out_8(®s->tx.dlr, frame->can_dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) out_8(®s->tx.tbpr, priv->cur_pri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Start transmission. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) out_8(®s->cantflg, 1 << buf_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!test_bit(F_TX_PROGRESS, &priv->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) can_put_echo_skb(skb, dev, buf_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Enable interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) priv->tx_active |= 1 << buf_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) out_8(®s->cantier, priv->tx_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static enum can_state get_new_state(struct net_device *dev, u8 canrflg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (unlikely(canrflg & MSCAN_CSCIF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return state_map[max(MSCAN_STATE_RX(canrflg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MSCAN_STATE_TX(canrflg))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return priv->can.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) can_id = in_be16(®s->rx.idr1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (can_id & (1 << 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) frame->can_id = CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) can_id = ((can_id & 0xffe00000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ((can_id & 0x7ffff) << 2)) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) can_id >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) frame->can_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) frame->can_id |= can_id >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (can_id & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) frame->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!(frame->can_id & CAN_RTR_FLAG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void __iomem *data = ®s->rx.dsr1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 *payload = (u16 *)frame->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (i = 0; i < frame->can_dlc / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *payload++ = in_be16(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) data += 2 + _MSCAN_RESERVED_DSR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* read remaining byte if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (frame->can_dlc & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) frame->data[frame->can_dlc - 1] = in_8(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) out_8(®s->canrflg, MSCAN_RXF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 canrflg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum can_state new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) netdev_dbg(dev, "error interrupt (canrflg=%#x)\n", canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) frame->can_id = CAN_ERR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (canrflg & MSCAN_OVRIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) frame->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stats->rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) frame->data[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) new_state = get_new_state(dev, canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (new_state != priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) can_change_state(dev, frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) state_map[MSCAN_STATE_TX(canrflg)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) state_map[MSCAN_STATE_RX(canrflg)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (priv->can.state == CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * The MSCAN on the MPC5200 does recover from bus-off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * automatically. To avoid that we stop the chip doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * a light-weight stop (we are in irq-context).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (priv->type != MSCAN_TYPE_MPC5121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) out_8(®s->cantier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) out_8(®s->canrier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) setbits8(®s->canctl0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MSCAN_SLPRQ | MSCAN_INITRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) can_bus_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) frame->can_dlc = CAN_ERR_DLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) out_8(®s->canrflg, MSCAN_ERR_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int mscan_rx_poll(struct napi_struct *napi, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct net_device *dev = napi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct can_frame *frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 canrflg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) while (work_done < quota) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) canrflg = in_8(®s->canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) skb = alloc_can_skb(dev, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) netdev_notice(dev, "packet dropped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) stats->rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) out_8(®s->canrflg, canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (canrflg & MSCAN_RXF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mscan_get_rx_frame(dev, frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else if (canrflg & MSCAN_ERR_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mscan_get_err_frame(dev, frame, canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) stats->rx_bytes += frame->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) work_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (work_done < quota) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (likely(napi_complete_done(&priv->napi, work_done))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clear_bit(F_RX_PROGRESS, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (priv->can.state < CAN_STATE_BUS_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) out_8(®s->canrier, priv->shadow_canrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static irqreturn_t mscan_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct net_device *dev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 cantier, cantflg, canrflg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cantier = in_8(®s->cantier) & MSCAN_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cantflg = in_8(®s->cantflg) & cantier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (cantier && cantflg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct list_head *tmp, *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) list_for_each_safe(pos, tmp, &priv->tx_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct tx_queue_entry *entry =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) list_entry(pos, struct tx_queue_entry, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 mask = entry->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!(cantflg & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) out_8(®s->cantbsel, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) stats->tx_bytes += in_8(®s->tx.dlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) can_get_echo_skb(dev, entry->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv->tx_active &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) list_del(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (list_empty(&priv->tx_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clear_bit(F_TX_WAIT_ALL, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clear_bit(F_TX_PROGRESS, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) priv->cur_pri = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) out_8(®s->cantier, priv->tx_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) canrflg = in_8(®s->canrflg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((canrflg & ~MSCAN_STAT_MSK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (canrflg & ~MSCAN_STAT_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) priv->shadow_canrier = in_8(®s->canrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) out_8(®s->canrier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) clear_bit(F_RX_PROGRESS, &priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = mscan_restart(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (netif_queue_stopped(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int mscan_do_set_bittiming(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 btr0, btr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BTR1_SET_TSEG2(bt->phase_seg2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) out_8(®s->canbtr0, btr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) out_8(®s->canbtr1, btr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mscan_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bec->txerr = in_8(®s->cantxerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) bec->rxerr = in_8(®s->canrxerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int mscan_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = clk_prepare_enable(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto exit_retcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = clk_prepare_enable(priv->clk_can);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) goto exit_dis_ipg_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* common open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = open_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto exit_dis_can_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) netdev_err(dev, "failed to attach interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto exit_napi_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) setbits8(®s->canctl1, MSCAN_LISTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clrbits8(®s->canctl1, MSCAN_LISTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = mscan_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) exit_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) exit_napi_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) exit_dis_can_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk_disable_unprepare(priv->clk_can);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) exit_dis_ipg_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) clk_disable_unprepare(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) exit_retcode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int mscan_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) out_8(®s->cantier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) out_8(®s->canrier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mscan_set_mode(dev, MSCAN_INIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) clk_disable_unprepare(priv->clk_can);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_disable_unprepare(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct net_device_ops mscan_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ndo_open = mscan_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .ndo_stop = mscan_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ndo_start_xmit = mscan_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int register_mscandev(struct net_device *dev, int mscan_clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ctl1 = in_8(®s->canctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (mscan_clksrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ctl1 |= MSCAN_CLKSRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ctl1 &= ~MSCAN_CLKSRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (priv->type == MSCAN_TYPE_MPC5121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) priv->can.do_get_berr_counter = mscan_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ctl1 |= MSCAN_CANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) out_8(®s->canctl1, ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* acceptance mask/acceptance code (accept everything) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) out_be16(®s->canidar1_0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) out_be16(®s->canidar3_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) out_be16(®s->canidar5_4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) out_be16(®s->canidar7_6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) out_be16(®s->canidmr1_0, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) out_be16(®s->canidmr3_2, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) out_be16(®s->canidmr5_4, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) out_be16(®s->canidmr7_6, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Two 32 bit Acceptance Filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) out_8(®s->canidac, MSCAN_AF_32BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mscan_set_mode(dev, MSCAN_INIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return register_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) void unregister_mscandev(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct mscan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct mscan_regs __iomem *regs = priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mscan_set_mode(dev, MSCAN_INIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clrbits8(®s->canctl1, MSCAN_CANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unregister_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct net_device *alloc_mscandev(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mscan_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev->netdev_ops = &mscan_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev->flags |= IFF_ECHO; /* we support local echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) priv->can.bittiming_const = &mscan_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) priv->can.do_set_bittiming = mscan_do_set_bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) priv->can.do_set_mode = mscan_do_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CAN_CTRLMODE_LISTENONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for (i = 0; i < TX_QUEUE_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) priv->tx_queue[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) priv->tx_queue[i].mask = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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