^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // flexcan.c - FLEXCAN CAN controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2005-2006 Varma Electronics Oy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (c) 2009 Sascha Hauer, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2014 David Jander, Protonic Holland
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/can.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/can/rx-offload.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRV_NAME "flexcan"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* 8 for RX fifo and 2 error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FLEXCAN_NAPI_WEIGHT (8 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* FLEXCAN module configuration register (CANMCR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FLEXCAN_MCR_MDIS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FLEXCAN_MCR_FRZ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FLEXCAN_MCR_FEN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FLEXCAN_MCR_HALT BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FLEXCAN_MCR_NOT_RDY BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FLEXCAN_MCR_WAK_MSK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FLEXCAN_MCR_SOFTRST BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FLEXCAN_MCR_FRZ_ACK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FLEXCAN_MCR_SUPV BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FLEXCAN_MCR_SLF_WAK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FLEXCAN_MCR_WRN_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FLEXCAN_MCR_LPM_ACK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FLEXCAN_MCR_WAK_SRC BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FLEXCAN_MCR_DOZE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FLEXCAN_MCR_SRX_DIS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FLEXCAN_MCR_IRMQ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FLEXCAN_MCR_LPRIO_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FLEXCAN_MCR_AEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FLEXCAN_MCR_FDEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* FLEXCAN control register (CANCTRL) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FLEXCAN_CTRL_ERR_MSK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FLEXCAN_CTRL_CLK_SRC BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FLEXCAN_CTRL_LPB BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FLEXCAN_CTRL_SMP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FLEXCAN_CTRL_BOFF_REC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FLEXCAN_CTRL_TSYN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FLEXCAN_CTRL_LBUF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FLEXCAN_CTRL_LOM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FLEXCAN_CTRL_ERR_STATE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FLEXCAN_CTRL_BOFF_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FLEXCAN_CTRL_ERR_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* FLEXCAN control register 2 (CTRL2) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FLEXCAN_CTRL2_ECRWRE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FLEXCAN_CTRL2_MRP BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FLEXCAN_CTRL2_RRS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FLEXCAN_CTRL2_EACEN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* FLEXCAN memory error control register (MECR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FLEXCAN_MECR_ECRWRDIS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FLEXCAN_MECR_CEI_MSK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FLEXCAN_MECR_HAERRIE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FLEXCAN_MECR_FAERRIE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FLEXCAN_MECR_EXTERRIE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FLEXCAN_MECR_RERRDIS BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FLEXCAN_MECR_ECCDIS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* FLEXCAN error and status register (ESR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FLEXCAN_ESR_TWRN_INT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FLEXCAN_ESR_RWRN_INT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FLEXCAN_ESR_BIT1_ERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FLEXCAN_ESR_BIT0_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FLEXCAN_ESR_ACK_ERR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FLEXCAN_ESR_CRC_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FLEXCAN_ESR_FRM_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FLEXCAN_ESR_STF_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FLEXCAN_ESR_TX_WRN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FLEXCAN_ESR_RX_WRN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FLEXCAN_ESR_IDLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FLEXCAN_ESR_TXRX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FLEXCAN_ESR_BOFF_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FLEXCAN_ESR_ERR_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FLEXCAN_ESR_WAK_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FLEXCAN_ESR_ERR_BUS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FLEXCAN_ESR_ERR_STATE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FLEXCAN_ESR_ERR_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FLEXCAN_ESR_ALL_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* FLEXCAN Bit Timing register (CBT) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FLEXCAN_CBT_BTF BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* FLEXCAN FD control register (FDCTRL) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FLEXCAN_FDCTRL_FDRATE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FLEXCAN_FDCTRL_MBDSR_8 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FLEXCAN_FDCTRL_MBDSR_12 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FLEXCAN_FDCTRL_MBDSR_32 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FLEXCAN_FDCTRL_MBDSR_64 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FLEXCAN_FDCTRL_TDCEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* FLEXCAN FD Bit Timing register (FDCBT) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* FLEXCAN interrupt flag register (IFLAG) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Errata ERR005829 step7: Reserve first valid MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* FLEXCAN message buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FLEXCAN_MB_CODE_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FLEXCAN_MB_CNT_EDL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FLEXCAN_MB_CNT_BRS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FLEXCAN_MB_CNT_ESI BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FLEXCAN_MB_CNT_SRR BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FLEXCAN_MB_CNT_IDE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FLEXCAN_MB_CNT_RTR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FLEXCAN_TIMEOUT_US (250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* FLEXCAN hardware feature flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Below is some version info we got:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Filter? connected? Passive detection ption in MB Supported?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * MX25 FlexCAN2 03.00.00.00 no no no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * MX28 FlexCAN2 03.00.04.00 yes yes no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * MX35 FlexCAN2 03.00.00.00 no no no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * MX53 FlexCAN2 03.00.00.00 yes no no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * VF610 FlexCAN3 ? no yes no yes yes? no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* [TR]WRN_INT not connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Disable RX FIFO Global mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Enable EACEN and RRS bit in ctrl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Disable non-correctable errors interrupt and freeze mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Use timestamp based offloading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* No interrupt for error passive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* default to BE register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Setup stop mode to support wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Support CAN-FD mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* support memory detection and correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Structure of the message buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct flexcan_mb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 can_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Structure of the hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct flexcan_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 mcr; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 ctrl; /* 0x04 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 timer; /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 tcr; /* 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 ecr; /* 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 esr; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 imask2; /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 imask1; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 iflag2; /* 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 iflag1; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) union { /* 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 gfwr_mx28; /* MX28, MX53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 esr2; /* 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 imeur; /* 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 lrfr; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 crcr; /* 0x44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 rxfgmask; /* 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 rxfir; /* 0x4c - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 cbt; /* 0x50 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 _reserved2; /* 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 dbg1; /* 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 dbg2; /* 0x5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 _reserved3[8]; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* FIFO-mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 0x080...0x08f 0 RX message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 0x090...0x0df 1-5 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 0x0e0...0x0ff 6-7 8 entry ID table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * (mx25, mx28, mx35, mx53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * 0x0e0...0x2df 6-7..37 8..128 entry ID table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * size conf'ed via ctrl2::RFFN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * (mx6, vf610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 _reserved4[256]; /* 0x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 _reserved5[24]; /* 0x980 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 gfwr_mx6; /* 0x9e0 - MX6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 _reserved6[39]; /* 0x9e4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 _rxfir[6]; /* 0xa80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 _reserved8[2]; /* 0xa98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 _rxmgmask; /* 0xaa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 _rxfgmask; /* 0xaa4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 _rx14mask; /* 0xaa8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 _rx15mask; /* 0xaac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 tx_smb[4]; /* 0xab0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 rx_smb0[4]; /* 0xac0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 rx_smb1[4]; /* 0xad0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 mecr; /* 0xae0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 erriar; /* 0xae4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 erridpr; /* 0xae8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 errippr; /* 0xaec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 rerrar; /* 0xaf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 rerrdr; /* 0xaf4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 rerrsynr; /* 0xaf8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 errsr; /* 0xafc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 _reserved7[64]; /* 0xb00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 fdcrc; /* 0xc08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 _reserved9[199]; /* 0xc0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 tx_smb_fd[18]; /* 0xf28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 rx_smb0_fd[18]; /* 0xf70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 rx_smb1_fd[18]; /* 0xfb8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct flexcan_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 quirks; /* quirks needed for different IP cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct flexcan_stop_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 req_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 req_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct flexcan_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct can_priv can;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct can_rx_offload offload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct flexcan_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct flexcan_mb __iomem *tx_mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct flexcan_mb __iomem *tx_mb_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 tx_mb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 mb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 mb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 clk_src; /* clock source of CAN Protocol Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u64 rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u64 tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 reg_ctrl_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const struct flexcan_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct regulator *reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct flexcan_stop_mode stm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Read and Write APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 (*read)(void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void (*write)(u32 val, void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FLEXCAN_QUIRK_BROKEN_PERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FLEXCAN_QUIRK_BROKEN_PERR_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FLEXCAN_QUIRK_SETUP_STOP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FLEXCAN_QUIRK_SUPPORT_FD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FLEXCAN_QUIRK_SUPPORT_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct can_bittiming_const flexcan_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .tseg1_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .brp_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct can_bittiming_const flexcan_fd_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .tseg1_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .tseg1_max = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .tseg2_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .sjw_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .brp_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .tseg1_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .tseg1_max = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .brp_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .brp_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* FlexCAN module is essentially modelled as a little-endian IP in most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * SoCs, i.e the registers as well as the message buffer areas are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * implemented in a little-endian fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * module in a big-endian fashion (i.e the registers as well as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * message buffer areas are implemented in a big-endian way).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * In addition, the FlexCAN module can be found on SoCs having ARM or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * PPC cores. So, we need to abstract off the register read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * functions, ensuring that these cater to all the combinations of module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * endianness and underlying CPU endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline u32 flexcan_read_be(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline void flexcan_write_be(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline u32 flexcan_read_le(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static inline void flexcan_write_le(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 mb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 bank_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bool bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (WARN_ON(mb_index >= priv->mb_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bank = mb_index >= bank_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mb_index -= bank_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return (struct flexcan_mb __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (&priv->regs->mb[bank][priv->mb_size * mb_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 reg_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reg_mcr = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) reg_mcr |= FLEXCAN_MCR_WAK_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv->write(reg_mcr, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 reg_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg_mcr = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) reg_mcr |= FLEXCAN_MCR_SLF_WAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) priv->write(reg_mcr, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* enable stop request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return flexcan_low_power_enter_ack(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 reg_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* remove stop request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 1 << priv->stm.req_bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) reg_mcr = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) priv->write(reg_mcr, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return flexcan_low_power_exit_ack(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) priv->write(reg_ctrl, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) priv->write(reg_ctrl, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int flexcan_clks_enable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) err = clk_prepare_enable(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) err = clk_prepare_enable(priv->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clk_disable_unprepare(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void flexcan_clks_disable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) clk_disable_unprepare(priv->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk_disable_unprepare(priv->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!priv->reg_xceiver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return regulator_enable(priv->reg_xceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!priv->reg_xceiver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return regulator_disable(priv->reg_xceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int flexcan_chip_enable(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) reg &= ~FLEXCAN_MCR_MDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) priv->write(reg, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return flexcan_low_power_exit_ack(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int flexcan_chip_disable(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) reg |= FLEXCAN_MCR_MDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) priv->write(reg, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return flexcan_low_power_enter_ack(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int flexcan_chip_freeze(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 bitrate = priv->can.bittiming.bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) timeout = 1000 * 1000 * 10 / bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) timeout = FLEXCAN_TIMEOUT_US / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) priv->write(reg, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) reg &= ~FLEXCAN_MCR_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) priv->write(reg, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int flexcan_chip_softreset(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int __flexcan_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) const struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 reg = priv->read(®s->ecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) bec->txerr = (reg >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) bec->rxerr = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int flexcan_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) const struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) err = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) err = __flexcan_get_berr_counter(dev, bec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pm_runtime_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (can_dropped_invalid_skb(dev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (cfd->can_id & CAN_EFF_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) can_id = cfd->can_id & CAN_EFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (cfd->can_id & CAN_RTR_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ctrl |= FLEXCAN_MB_CNT_RTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (can_is_canfd_skb(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ctrl |= FLEXCAN_MB_CNT_EDL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (cfd->flags & CANFD_BRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ctrl |= FLEXCAN_MB_CNT_BRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) for (i = 0; i < cfd->len; i += sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) data = be32_to_cpup((__be32 *)&cfd->data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) can_put_echo_skb(skb, dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) priv->write(can_id, &priv->tx_mb->can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) priv->write(ctrl, &priv->tx_mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Errata ERR005829 step8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Write twice INACTIVE(0x8) code to first MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &priv->tx_mb_reserved->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &priv->tx_mb_reserved->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) bool rx_errors = false, tx_errors = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) timestamp = priv->read(®s->timer) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) netdev_dbg(dev, "BIT1_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) cf->data[2] |= CAN_ERR_PROT_BIT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) tx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) netdev_dbg(dev, "BIT0_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cf->data[2] |= CAN_ERR_PROT_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) netdev_dbg(dev, "ACK_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) cf->can_id |= CAN_ERR_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cf->data[3] = CAN_ERR_PROT_LOC_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) netdev_dbg(dev, "CRC_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) netdev_dbg(dev, "FRM_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) rx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (reg_esr & FLEXCAN_ESR_STF_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) netdev_dbg(dev, "STF_ERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) rx_errors = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (rx_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (tx_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) enum can_state new_state, rx_state, tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct can_berr_counter bec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) new_state = max(tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __flexcan_get_berr_counter(dev, &bec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* state hasn't changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (likely(new_state == priv->can.state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) timestamp = priv->read(®s->timer) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) can_change_state(dev, cf, tx_state, rx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (unlikely(new_state == CAN_STATE_BUS_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) can_bus_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u64 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (upper_32_bits(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) reg = (u64)priv->read(addr - 4) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (lower_32_bits(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) reg |= priv->read(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return reg & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (upper_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) priv->write(upper_32_bits(val), addr - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (lower_32_bits(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) priv->write(lower_32_bits(val), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return container_of(offload, struct flexcan_priv, offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned int n, u32 *timestamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) bool drop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct flexcan_priv *priv = rx_offload_to_priv(offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct flexcan_mb __iomem *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct canfd_frame *cfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 reg_ctrl, reg_id, reg_iflag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (unlikely(drop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) skb = ERR_PTR(-ENOBUFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto mark_as_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mb = flexcan_get_mb(priv, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) reg_ctrl = priv->read(&mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* is this MB empty? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) (code != FLEXCAN_MB_CODE_RX_OVERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* This MB was overrun, we lost data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) offload->dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) offload->dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) reg_iflag1 = priv->read(®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) reg_ctrl = priv->read(&mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) skb = alloc_canfd_skb(offload->dev, &cfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) skb = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto mark_as_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* increase timstamp to full 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) *timestamp = reg_ctrl << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) reg_id = priv->read(&mb->can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) cfd->flags |= CANFD_BRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) cfd->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) cfd->flags |= CANFD_ESI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 0; i < cfd->len; i += sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) *(__be32 *)(cfd->data + i) = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mark_as_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Read the Free Running Timer. It is optional but recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * to unlock Mailbox as soon as possible and make it available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * for reception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) priv->read(®s->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static irqreturn_t flexcan_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) irqreturn_t handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u64 reg_iflag_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 reg_esr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) enum can_state last_state = priv->can.state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* reception interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u64 reg_iflag_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) reg_iflag_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 reg_iflag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) reg_iflag1 = priv->read(®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) can_rx_offload_irq_offload_fifo(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* FIFO overflow interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* transmission complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (reg_iflag_tx & priv->tx_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) 0, reg_ctrl << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) can_led_event(dev, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* after sending a RTR frame MB is in RX mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) &priv->tx_mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) reg_esr = priv->read(®s->esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* ACK all bus error, state change and wake IRQ sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* state change interrupt or broken error state quirk fix is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) flexcan_irq_state(dev, reg_esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* bus error IRQ - handle if bus error reporting is activated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) flexcan_irq_bus_err(dev, reg_esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* availability of error interrupt among state transitions in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * bus error reporting is de-activated and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * +--------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * | +----------------------------------------------+ [stopped / |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * | | | sleeping] -+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * +-+-> active <-> warning <-> passive -> bus off -+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * ___________^^^^^^^^^^^^_______________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * disabled(1) enabled disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if ((last_state != priv->can.state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) switch (priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case CAN_STATE_ERROR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (priv->devtype_data->quirks &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) FLEXCAN_QUIRK_BROKEN_WERR_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) flexcan_error_irq_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) flexcan_error_irq_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case CAN_STATE_ERROR_WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) flexcan_error_irq_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case CAN_STATE_ERROR_PASSIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case CAN_STATE_BUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) flexcan_error_irq_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) const struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) const struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) reg = priv->read(®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) FLEXCAN_CTRL_RJW(0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) FLEXCAN_CTRL_PSEG1(0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) FLEXCAN_CTRL_PSEG2(0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) FLEXCAN_CTRL_PROPSEG(0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) FLEXCAN_CTRL_RJW(bt->sjw - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) priv->write(reg, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* print chip status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) priv->read(®s->mcr), priv->read(®s->ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static void flexcan_set_bittiming_cbt(const struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct can_bittiming *dbt = &priv->can.data_bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) u32 reg_cbt, reg_fdctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* CBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * long. The can_calc_bittiming() tries to divide the tseg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * equally between phase_seg1 and prop_seg, which may not fit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * in CBT register. Therefore, if phase_seg1 is more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * possible value, increase prop_seg and decrease phase_seg1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (bt->phase_seg1 > 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bt->prop_seg += (bt->phase_seg1 - 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) bt->phase_seg1 = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) reg_cbt = FLEXCAN_CBT_BTF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) priv->write(reg_cbt, ®s->cbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u32 reg_fdcbt, reg_ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (bt->brp != dbt->brp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dbt->brp, bt->brp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* FDCBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * 5 bit long. The can_calc_bittiming tries to divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * the tseg1 equally between phase_seg1 and prop_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * which may not fit in FDCBT register. Therefore, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * phase_seg1 is more than possible value, increase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * prop_seg and decrease phase_seg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (dbt->phase_seg1 > 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dbt->prop_seg += (dbt->phase_seg1 - 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dbt->phase_seg1 = 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) reg_fdcbt = priv->read(®s->fdcbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) priv->write(reg_fdcbt, ®s->fdcbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) reg_ctrl2 = priv->read(®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* FDCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) reg_fdctrl = priv->read(®s->fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* TDC must be disabled for Loop Back mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ((dbt->phase_seg1 - 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dbt->prop_seg + 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ((dbt->brp - 1 ) + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) priv->write(reg_fdctrl, ®s->fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) priv->read(®s->mcr), priv->read(®s->ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) priv->read(®s->ctrl2), priv->read(®s->fdctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) priv->read(®s->cbt), priv->read(®s->fdcbt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static void flexcan_set_bittiming(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) const struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) reg = priv->read(®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) FLEXCAN_CTRL_LOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) reg |= FLEXCAN_CTRL_LPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) reg |= FLEXCAN_CTRL_LOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) reg |= FLEXCAN_CTRL_SMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) priv->write(reg, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return flexcan_set_bittiming_cbt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return flexcan_set_bittiming_ctrl(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static void flexcan_ram_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u32 reg_ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* 11.8.3.13 Detection and correction of memory errors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * CTRL2[WRMFRZ] grants write access to all memory positions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * that require initialization, ranging from 0x080 to 0xADF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * need to be initialized as well. MCR[RFEN] must not be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * during memory initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) reg_ctrl2 = priv->read(®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) memset_io(®s->mb[0][0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) offsetof(struct flexcan_regs, rx_smb1[3]) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) memset_io(®s->tx_smb_fd[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* flexcan_chip_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * this functions is entered with clocks enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static int flexcan_chip_start(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u64 reg_imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct flexcan_mb __iomem *mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* enable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) err = flexcan_chip_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) err = flexcan_chip_softreset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) flexcan_ram_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) flexcan_set_bittiming(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* set freeze, halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) err = flexcan_chip_freeze(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* MCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * only supervisor access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * enable warning int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * enable individual RX masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * choose format C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * set max mailbox number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) reg_mcr = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* MCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * - disable for timestamp mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * - enable for FIFO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) reg_mcr &= ~FLEXCAN_MCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) reg_mcr |= FLEXCAN_MCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* MCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * asserted because this will impede the self reception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * of a transmitted message. This is not documented in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * earlier versions of flexcan block guide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * Self Reception:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * - enable Self Reception for loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * (by clearing "Self Reception Disable" bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * - disable for normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) reg_mcr |= FLEXCAN_MCR_SRX_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* MCR - CAN-FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) reg_mcr |= FLEXCAN_MCR_FDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) reg_mcr &= ~FLEXCAN_MCR_FDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) priv->write(reg_mcr, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * disable timer sync feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * disable auto busoff recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * transmit lowest buffer first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * enable tx and rx warning interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * enable bus off interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * (== FLEXCAN_CTRL_ERR_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) reg_ctrl = priv->read(®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) FLEXCAN_CTRL_ERR_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * on most Flexcan cores, too. Otherwise we don't get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * any error warning or passive interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* save for later use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) priv->reg_ctrl_default = reg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* leave interrupts disabled for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) priv->write(reg_ctrl, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) reg_ctrl2 = priv->read(®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u32 reg_fdctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) reg_fdctrl = priv->read(®s->fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) reg_fdctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) FLEXCAN_FDCTRL_MBDSR_64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) FLEXCAN_FDCTRL_MBDSR_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) reg_fdctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) FLEXCAN_FDCTRL_MBDSR_8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) FLEXCAN_FDCTRL_MBDSR_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) __func__, reg_fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) priv->write(reg_fdctrl, ®s->fdctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) mb = flexcan_get_mb(priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) &mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* clear and invalidate unused mailboxes first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) mb = flexcan_get_mb(priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) &mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* Errata ERR005829: mark first TX mailbox as INACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) &priv->tx_mb_reserved->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* mark TX mailbox as INACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) &priv->tx_mb->can_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* acceptance mask/acceptance code (accept everything) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) priv->write(0x0, ®s->rxgmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) priv->write(0x0, ®s->rx14mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) priv->write(0x0, ®s->rx15mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) priv->write(0x0, ®s->rxfgmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* clear acceptance filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) for (i = 0; i < priv->mb_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) priv->write(0, ®s->rximr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* On Vybrid, disable non-correctable errors interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * freeze mode. It still can correct the correctable errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * when HW supports ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * This also works around errata e5295 which generates false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * positive memory errors and put the device in freeze mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* Follow the protocol as described in "Detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * and Correction of Memory Errors" to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * MECR register (step 1 - 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * 2. set CTRL2[ECRWRE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) reg_ctrl2 = priv->read(®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* 3. clear MECR[ECRWRDIS] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) reg_mecr = priv->read(®s->mecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) priv->write(reg_mecr, ®s->mecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) FLEXCAN_MECR_FANCEI_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) priv->write(reg_mecr, ®s->mecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* 5. after configuration done, lock MECR by either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) priv->write(reg_mecr, ®s->mecr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) priv->write(reg_ctrl2, ®s->ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* synchronize with the can bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err = flexcan_chip_unfreeze(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* enable interrupts atomically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) priv->write(priv->reg_ctrl_default, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) reg_imask = priv->rx_mask | priv->tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) priv->write(upper_32_bits(reg_imask), ®s->imask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) priv->write(lower_32_bits(reg_imask), ®s->imask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* print chip status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) priv->read(®s->mcr), priv->read(®s->ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) out_chip_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) flexcan_chip_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* __flexcan_chip_stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * this function is entered with clocks enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* freeze + disable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) err = flexcan_chip_freeze(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (err && !disable_on_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) err = flexcan_chip_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (err && !disable_on_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) goto out_chip_unfreeze;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) priv->write(0, ®s->imask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) priv->write(0, ®s->imask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) priv->can.state = CAN_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) out_chip_unfreeze:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) flexcan_chip_unfreeze(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return __flexcan_chip_stop(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static inline int flexcan_chip_stop(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return __flexcan_chip_stop(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static int flexcan_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) err = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) err = open_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) goto out_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) err = flexcan_transceiver_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) goto out_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) goto out_transceiver_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) (sizeof(priv->regs->mb[1]) / priv->mb_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) priv->tx_mb_reserved =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) priv->tx_mb_reserved =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) priv->tx_mb_idx = priv->mb_count - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) priv->offload.mailbox_read = flexcan_mailbox_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) priv->offload.mb_last = priv->mb_count - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) priv->offload.mb_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) err = can_rx_offload_add_timestamp(dev, &priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) err = can_rx_offload_add_fifo(dev, &priv->offload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) FLEXCAN_NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* start chip and queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) err = flexcan_chip_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto out_offload_del;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) can_led_event(dev, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) can_rx_offload_enable(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) out_offload_del:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) can_rx_offload_del(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) out_transceiver_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) flexcan_transceiver_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) out_close:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) out_runtime_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) pm_runtime_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static int flexcan_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) can_rx_offload_disable(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) flexcan_chip_stop_disable_on_error(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) can_rx_offload_del(&priv->offload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) flexcan_transceiver_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) pm_runtime_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) can_led_event(dev, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) err = flexcan_chip_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const struct net_device_ops flexcan_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .ndo_open = flexcan_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .ndo_stop = flexcan_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .ndo_start_xmit = flexcan_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static int register_flexcandev(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct flexcan_regs __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) u32 reg, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) err = flexcan_clks_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* select "bus clock", chip must be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) err = flexcan_chip_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) goto out_clks_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) reg = priv->read(®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (priv->clk_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) reg |= FLEXCAN_CTRL_CLK_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) reg &= ~FLEXCAN_CTRL_CLK_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) priv->write(reg, ®s->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) err = flexcan_chip_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* set freeze, halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) err = flexcan_chip_freeze(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* activate FIFO, restrict register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) priv->write(reg, ®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* Currently we only support newer versions of this core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * featuring a RX hardware FIFO (although this driver doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * make use of it on some cores). Older cores, found on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * Coldfire derivates are not tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) reg = priv->read(®s->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (!(reg & FLEXCAN_MCR_FEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) err = register_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) goto out_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* Disable core and let pm_runtime_put() disable the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * If CONFIG_PM is not enabled, the clocks will stay powered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) flexcan_chip_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) pm_runtime_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) out_chip_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) flexcan_chip_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) out_clks_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) flexcan_clks_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static void unregister_flexcandev(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) unregister_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static int flexcan_setup_stop_mode(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct device_node *gpr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) struct flexcan_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) phandle phandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) u32 out_val[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* stop mode property format is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * <&gpr req_gpr req_bit>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ARRAY_SIZE(out_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_dbg(&pdev->dev, "no stop-mode property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) phandle = *out_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) gpr_np = of_find_node_by_phandle(phandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (!gpr_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) priv->stm.gpr = syscon_node_to_regmap(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (IS_ERR(priv->stm.gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) dev_dbg(&pdev->dev, "could not find gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ret = PTR_ERR(priv->stm.gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) priv->stm.req_gpr = out_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) priv->stm.req_bit = out_val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) "gpr %s req_gpr=0x02%x req_bit=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) device_set_wakeup_capable(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (of_property_read_bool(np, "wakeup-source"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) device_set_wakeup_enable(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) out_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) of_node_put(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static const struct of_device_id flexcan_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) MODULE_DEVICE_TABLE(of, flexcan_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static const struct platform_device_id flexcan_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) MODULE_DEVICE_TABLE(platform, flexcan_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static int flexcan_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) const struct flexcan_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct flexcan_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct regulator *reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct clk *clk_ipg = NULL, *clk_per = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) struct flexcan_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) u8 clk_src = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) u32 clock_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) else if (PTR_ERR(reg_xceiver) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) reg_xceiver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) else if (IS_ERR(reg_xceiver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return PTR_ERR(reg_xceiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "clock-frequency", &clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) of_property_read_u8(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) "fsl,clk-source", &clk_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (!clock_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (IS_ERR(clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) dev_err(&pdev->dev, "no ipg clock defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) return PTR_ERR(clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (IS_ERR(clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_err(&pdev->dev, "no per clock defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return PTR_ERR(clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) clock_freq = clk_get_rate(clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) of_id = of_match_device(flexcan_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) devtype_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) } else if (platform_get_device_id(pdev)->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) devtype_data = (struct flexcan_devtype_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) dev = alloc_candev(sizeof(struct flexcan_priv), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dev->netdev_ops = &flexcan_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) priv->read = flexcan_read_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) priv->write = flexcan_write_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) priv->read = flexcan_read_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) priv->write = flexcan_write_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) priv->can.clock.freq = clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) priv->can.do_set_mode = flexcan_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) priv->can.do_get_berr_counter = flexcan_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) CAN_CTRLMODE_BERR_REPORTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) priv->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) priv->clk_ipg = clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) priv->clk_per = clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) priv->clk_src = clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) priv->devtype_data = devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) priv->reg_xceiver = reg_xceiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) CAN_CTRLMODE_FD_NON_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) priv->can.bittiming_const = &flexcan_fd_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) priv->can.data_bittiming_const =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) &flexcan_fd_data_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) priv->can.bittiming_const = &flexcan_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) err = register_flexcandev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_err(&pdev->dev, "registering netdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) goto failed_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) of_can_transceiver(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) devm_can_led_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) err = flexcan_setup_stop_mode(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) failed_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static int flexcan_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) device_set_wakeup_enable(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) device_set_wakeup_capable(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) unregister_flexcandev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static int __maybe_unused flexcan_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* if wakeup is enabled, enter stop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * else enter disabled mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (device_may_wakeup(device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) enable_irq_wake(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) err = flexcan_enter_stop_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) err = flexcan_chip_stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) err = pinctrl_pm_select_sleep_state(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) priv->can.state = CAN_STATE_SLEEPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) static int __maybe_unused flexcan_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (device_may_wakeup(device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) disable_irq_wake(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) err = flexcan_exit_stop_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) err = pinctrl_pm_select_default_state(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) err = flexcan_chip_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static int __maybe_unused flexcan_runtime_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) flexcan_clks_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static int __maybe_unused flexcan_runtime_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) return flexcan_clks_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static int __maybe_unused flexcan_noirq_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (device_may_wakeup(device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) flexcan_enable_wakeup_irq(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) err = pm_runtime_force_suspend(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static int __maybe_unused flexcan_noirq_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct flexcan_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) err = pm_runtime_force_resume(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (device_may_wakeup(device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) flexcan_enable_wakeup_irq(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static const struct dev_pm_ops flexcan_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static struct platform_driver flexcan_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .pm = &flexcan_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .of_match_table = flexcan_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .probe = flexcan_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .remove = flexcan_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .id_table = flexcan_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) module_platform_driver(flexcan_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) "Marc Kleine-Budde <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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