Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Core driver for the CC770 and AN82527 CAN controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009, 2011 Wolfgang Grandegger <wg@grandegger.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef CC770_DEV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define CC770_DEV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct cc770_msgobj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	u8 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u8 id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u8 data[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8 dontuse;		/* padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct cc770_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		struct cc770_msgobj msgobj[16]; /* Message object 1..15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			u8 control;		/* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			u8 status;		/* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			u8 cpu_interface;	/* CPU Interface Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			u8 dontuse1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			u8 high_speed_read[2];	/* High Speed Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			u8 global_mask_std[2];	/* Standard Global Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			u8 global_mask_ext[4];	/* Extended Global Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			u8 msg15_mask[4];	/* Message 15 Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			u8 dontuse2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			u8 clkout;		/* Clock Out Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			u8 dontuse3[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			u8 bus_config;		/* Bus Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			u8 dontuse4[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			u8 bit_timing_0;	/* Bit Timing Register byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			u8 dontuse5[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			u8 bit_timing_1;	/* Bit Timing Register byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			u8 dontuse6[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			u8 interrupt;		/* Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			u8 dontuse7[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			u8 rx_error_counter;	/* Receive Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			u8 dontuse8[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			u8 tx_error_counter;	/* Transmit Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			u8 dontuse9[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			u8 p1_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			u8 dontuse10[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			u8 p2_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			u8 dontuse11[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			u8 p1_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			u8 dontuse12[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			u8 p2_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			u8 dontuse13[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			u8 p1_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			u8 dontuse14[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			u8 p2_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			u8 dontuse15[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			u8 serial_reset_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Control Register (0x00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CTRL_INI	0x01	/* Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CTRL_IE		0x02	/* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CTRL_SIE	0x04	/* Status Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CTRL_EIE	0x08	/* Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CTRL_EAF	0x20	/* Enable additional functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CTRL_CCE	0x40	/* Change Configuration Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Status Register (0x01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define STAT_LEC_STUFF	0x01	/* Stuff error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define STAT_LEC_FORM	0x02	/* Form error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define STAT_LEC_ACK	0x03	/* Acknowledgement error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define STAT_LEC_BIT1	0x04	/* Bit1 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define STAT_LEC_BIT0	0x05	/* Bit0 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define STAT_LEC_CRC	0x06	/* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define STAT_LEC_MASK	0x07	/* Last Error Code mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define STAT_TXOK	0x08	/* Transmit Message Successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define STAT_RXOK	0x10	/* Receive Message Successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define STAT_WAKE	0x20	/* Wake Up Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define STAT_WARN	0x40	/* Warning Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define STAT_BOFF	0x80	/* Bus Off Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * CPU Interface Register (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Clock Out Register (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * Bus Configuration Register (0x2f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * see include/linux/can/platform/cc770.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Message Control Register 0 (Base Address + 0x0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define INTPND_RES	0x01	/* No Interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define INTPND_SET	0x02	/* Interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define INTPND_UNC	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RXIE_RES	0x04	/* Receive Interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RXIE_SET	0x08	/* Receive Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RXIE_UNC	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TXIE_RES	0x10	/* Transmit Interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TXIE_SET	0x20	/* Transmit Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TXIE_UNC	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSGVAL_RES	0x40	/* Message Invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSGVAL_SET	0x80	/* Message Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSGVAL_UNC	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Message Control Register 1 (Base Address + 0x01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NEWDAT_RES	0x01	/* No New Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NEWDAT_SET	0x02	/* New Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NEWDAT_UNC	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSGLST_RES	0x04	/* No Message Lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSGLST_SET	0x08	/* Message Lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSGLST_UNC	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CPUUPD_RES	0x04	/* No CPU Updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CPUUPD_SET	0x08	/* CPU Updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CPUUPD_UNC	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TXRQST_RES	0x10	/* No Transmission Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TXRQST_SET	0x20	/* Transmission Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TXRQST_UNC	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RMTPND_RES	0x40	/* No Remote Request Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RMTPND_SET	0x80	/* Remote Request Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RMTPND_UNC	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Message Configuration Register (Base Address + 0x06) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSGCFG_XTD	0x04	/* Extended Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MSGCFG_DIR	0x08	/* Direction is Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MSGOBJ_FIRST	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSGOBJ_LAST	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CC770_IO_SIZE	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CC770_MAX_IRQ	20	/* max. number of interrupts handled in ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CC770_MAX_MSG	4	/* max. number of messages handled in ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CC770_ECHO_SKB_MAX	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define cc770_read_reg(priv, member)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	priv->read_reg(priv, offsetof(struct cc770_regs, member))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define cc770_write_reg(priv, member, value)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * Message objects and flags used by this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CC770_OBJ_FLAG_RX	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CC770_OBJ_FLAG_RTR	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CC770_OBJ_FLAG_EFF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	CC770_OBJ_RX0 = 0,	/* for receiving normal messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	CC770_OBJ_RX1,		/* for receiving normal messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	CC770_OBJ_RX_RTR0,	/* for receiving remote transmission requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	CC770_OBJ_RX_RTR1,	/* for receiving remote transmission requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	CC770_OBJ_TX,		/* for sending messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	CC770_OBJ_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define obj2msgobj(o)	(MSGOBJ_LAST - (o)) /* message object 11..15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * CC770 private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct cc770_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct can_priv can;	/* must be the first member */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct sk_buff *echo_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* the lower-layer is responsible for appropriate locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 (*read_reg)(const struct cc770_priv *priv, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	void (*pre_irq)(const struct cc770_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	void (*post_irq)(const struct cc770_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	void *priv;		/* for board-specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	void __iomem *reg_base;	 /* ioremap'ed address to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned long irq_flags; /* for request_irq() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned char obj_flags[CC770_OBJ_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u8 control_normal_mode;	/* Control register for normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u8 cpu_interface;	/* CPU interface register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8 clkout;		/* Clock out register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u8 bus_config;		/* Bus configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct net_device *alloc_cc770dev(int sizeof_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void free_cc770dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int register_cc770dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void unregister_cc770dev(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif /* CC770_DEV_H */