^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * at91_can.c - CAN network driver for AT91 SoC CAN controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/if_arp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtnetlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/can/dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/can/error.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/can/led.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_MB_MASK(i) ((1 << (i)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum at91_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) AT91_MR = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) AT91_IER = 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AT91_IDR = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) AT91_IMR = 0x00C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) AT91_SR = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) AT91_BR = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) AT91_TIM = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) AT91_TIMESTP = 0x01C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) AT91_ECR = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AT91_TCR = 0x024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AT91_ACR = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Mailbox registers (0 <= i <= 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_MR_CANEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AT91_MR_LPM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_MR_ABM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_MR_OVL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_MR_TEOF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AT91_MR_TTM BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AT91_MR_TIMFRZ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AT91_MR_DRPT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AT91_SR_RBSY BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AT91_MMR_PRIO_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AT91_MID_MIDE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AT91_MSR_MRTR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AT91_MSR_MABT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AT91_MSR_MRDY BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AT91_MSR_MMI BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AT91_MCR_MRTR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AT91_MCR_MTCR BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Mailbox Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum at91_mb_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) AT91_MB_MODE_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) AT91_MB_MODE_RX = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) AT91_MB_MODE_RX_OVRWR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AT91_MB_MODE_TX = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AT91_MB_MODE_CONSUMER = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AT91_MB_MODE_PRODUCER = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Interrupt mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AT91_IRQ_ERRA (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AT91_IRQ_WARN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AT91_IRQ_ERRP (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AT91_IRQ_BOFF (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AT91_IRQ_SLEEP (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AT91_IRQ_WAKEUP (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AT91_IRQ_TOVF (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AT91_IRQ_TSTP (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AT91_IRQ_CERR (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AT91_IRQ_SERR (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AT91_IRQ_AERR (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AT91_IRQ_FERR (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AT91_IRQ_BERR (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AT91_IRQ_ERR_ALL (0x1fff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AT91_IRQ_ERRP | AT91_IRQ_BOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AT91_IRQ_ALL (0x1fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum at91_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) AT91_DEVTYPE_SAM9263,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) AT91_DEVTYPE_SAM9X5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct at91_devtype_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int rx_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int rx_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int rx_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int tx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum at91_devtype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct at91_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct can_priv can; /* must be the first member! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 reg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int tx_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int tx_echo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int rx_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct at91_devtype_data devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct at91_can_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) canid_t mb0_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct at91_devtype_data at91_at91sam9263_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .rx_first = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .rx_split = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .rx_last = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .tx_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .type = AT91_DEVTYPE_SAM9263,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct at91_devtype_data at91_at91sam9x5_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .rx_first = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .rx_split = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .rx_last = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .tx_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .type = AT91_DEVTYPE_SAM9X5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct can_bittiming_const at91_bittiming_const = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .tseg1_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .tseg1_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .tseg2_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .tseg2_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .sjw_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .brp_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .brp_max = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .brp_inc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AT91_IS(_model) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline int at91_is_sam##_model(const struct at91_priv *priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) AT91_IS(9263);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) AT91_IS(9X5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return priv->devtype_data.rx_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return priv->devtype_data.rx_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return priv->devtype_data.rx_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return get_mb_rx_split(priv) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return AT91_MB_MASK(get_mb_rx_split(priv)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ~AT91_MB_MASK(get_mb_rx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return priv->devtype_data.tx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 1 << get_mb_tx_shift(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return get_mb_rx_last(priv) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return get_mb_tx_shift(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0xf << get_mb_tx_shift(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return AT91_MB_MASK(get_mb_tx_shift(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline unsigned int get_next_mask(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return get_next_mb_mask(priv) | get_next_prio_mask(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ~AT91_MB_MASK(get_mb_rx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ~AT91_MB_MASK(get_mb_tx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return readl_relaxed(priv->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(value, priv->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline void set_mb_mode_prio(const struct at91_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int mb, enum at91_mb_mode mode, int prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) enum at91_mb_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) set_mb_mode_prio(priv, mb, mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 reg_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (can_id & CAN_EFF_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg_mid = (can_id & CAN_SFF_MASK) << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return reg_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void at91_setup_mailboxes(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 reg_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * mailbox is disabled. The next 11 mailboxes are used as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * reception FIFO. The last mailbox is configured with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * overwrite option. The overwrite flag indicates a FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (i = 0; i < get_mb_rx_first(priv); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) at91_write(priv, AT91_MID(i), reg_mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) set_mb_mode(priv, i, AT91_MB_MODE_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* reset acceptance mask and id register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) at91_write(priv, AT91_MAM(i), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* The last 4 mailboxes are used for transmitting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Reset tx and rx helper pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) priv->tx_next = priv->tx_echo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) priv->rx_next = get_mb_rx_first(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int at91_set_bittiming(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct can_bittiming *bt = &priv->can.bittiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 reg_br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ((bt->phase_seg2 - 1) << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) at91_write(priv, AT91_BR, reg_br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int at91_get_berr_counter(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct can_berr_counter *bec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 reg_ecr = at91_read(priv, AT91_ECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bec->rxerr = reg_ecr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bec->txerr = reg_ecr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void at91_chip_start(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 reg_mr, reg_ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* disable chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) reg_mr = at91_read(priv, AT91_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) at91_set_bittiming(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) at91_setup_mailboxes(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* enable chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg_mr = AT91_MR_CANEN | AT91_MR_ABM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg_mr = AT91_MR_CANEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) at91_write(priv, AT91_MR, reg_mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) priv->can.state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) at91_write(priv, AT91_IER, reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void at91_chip_stop(struct net_device *dev, enum can_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 reg_mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) reg_mr = at91_read(priv, AT91_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) priv->can.state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * theory of operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * According to the datasheet priority 0 is the highest priority, 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * is the lowest. If two mailboxes have the same priority level the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * message of the mailbox with the lowest number is sent first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * the next mailbox with prio 0, and so on, until all mailboxes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * used. Then we start from the beginning with mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * prio 1. When we reach the last mailbox with prio 15, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * stop sending, waiting for all messages to be delivered, then start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * again with mailbox AT91_MB_TX_FIRST prio 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * We use the priv->tx_next as counter for the next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * encode the mailbox number, the upper 4 bits the mailbox priority:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * priv->tx_next = (prio << get_next_prio_shift(priv)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * (mb - get_mb_tx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct can_frame *cf = (struct can_frame *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int mb, prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 reg_mid, reg_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (can_dropped_invalid_skb(dev, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mb = get_tx_next_mb(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) prio = get_tx_next_prio(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reg_mid = at91_can_id_to_reg_mid(cf->can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) (cf->can_dlc << 16) | AT91_MCR_MTCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* disable MB while writing ID (see datasheet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) at91_write(priv, AT91_MID(mb), reg_mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* This triggers transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) at91_write(priv, AT91_MCR(mb), reg_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) stats->tx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * we have to stop the queue and deliver all messages in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * of a prio+mb counter wrap around. This is the case if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * tx_next buffer prio and mailbox equals 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * also stop the queue if next buffer is still in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * (== not ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) priv->tx_next++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) AT91_MSR_MRDY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (priv->tx_next & get_next_mask(priv)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Enable interrupt for this mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) at91_write(priv, AT91_IER, 1 << mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * at91_activate_rx_low - activate lower rx mailboxes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @priv: a91 context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Reenables the lower mailboxes for reception of new CAN messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static inline void at91_activate_rx_low(const struct at91_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 mask = get_mb_rx_low_mask(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) at91_write(priv, AT91_TCR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * at91_activate_rx_mb - reactive single rx mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * @priv: a91 context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * @mb: mailbox to reactivate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Reenables given mailbox for reception of new CAN messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline void at91_activate_rx_mb(const struct at91_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 mask = 1 << mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) at91_write(priv, AT91_TCR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * at91_rx_overflow_err - send error frame due to rx overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void at91_rx_overflow_err(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) netdev_dbg(dev, "RX buffer overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) stats->rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) stats->rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @mb: mailbox number to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * @cf: can frame where to store message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Reads a CAN message from the given mailbox and stores data into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * given can frame. "mb" and "cf" must be valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void at91_read_mb(struct net_device *dev, unsigned int mb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct can_frame *cf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 reg_msr, reg_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) reg_mid = at91_read(priv, AT91_MID(mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (reg_mid & AT91_MID_MIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) reg_msr = at91_read(priv, AT91_MSR(mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (reg_msr & AT91_MSR_MRTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) cf->can_id |= CAN_RTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* allow RX of extended frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) at91_rx_overflow_err(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * at91_read_msg - read CAN message from mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @mb: mail box to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Reads a CAN message from given mailbox, and put into linux network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * RX queue, does all housekeeping chores (stats, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void at91_read_msg(struct net_device *dev, unsigned int mb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct net_device_stats *stats = &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) skb = alloc_can_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) stats->rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) at91_read_mb(dev, mb, cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) stats->rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) stats->rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) can_led_event(dev, CAN_LED_EVENT_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * at91_poll_rx - read multiple CAN messages from mailboxes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * @dev: net device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * @quota: max number of pkgs we're allowed to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * Theory of Operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * on the chip are reserved for RX. We split them into 2 groups. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Like it or not, but the chip always saves a received CAN message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * into the first free mailbox it finds (starting with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * lowest). This makes it very difficult to read the messages in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * right order from the chip. This is how we work around that problem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * The first message goes into mb nr. 1 and issues an interrupt. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * rx ints are disabled in the interrupt handler and a napi poll is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * scheduled. We read the mailbox, but do _not_ re-enable the mb (to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * receive another message).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * lower mbxs upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * ____^______ __^__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * / \ / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * +-+-+-+-+-+-+-+-++-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * | |x|x|x|x|x|x|x|| | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * +-+-+-+-+-+-+-+-++-+-+-+-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * 0 1 2 3 4 5 6 7 8 9 0 1 / box
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * unused, due to chip bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * The variable priv->rx_next points to the next mailbox to read a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * message from. As long we're in the lower mailboxes we just read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * mailbox but not re-enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * With completion of the last of the lower mailboxes, we re-enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * whole first group, but continue to look for filled mailboxes in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * upper mailboxes. Imagine the second group like overflow mailboxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * which takes CAN messages if the lower goup is full. While in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * upper group we re-enable the mailbox right after reading it. Giving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * the chip more room to store messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * After finishing we look again in the lower group if we've still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * quota.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int at91_poll_rx(struct net_device *dev, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 reg_sr = at91_read(priv, AT91_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) const unsigned long *addr = (unsigned long *)®_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (priv->rx_next > get_mb_rx_low_last(priv) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) reg_sr & get_mb_rx_low_mask(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) netdev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "order of incoming frames cannot be guaranteed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mb < get_mb_tx_first(priv) && quota > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reg_sr = at91_read(priv, AT91_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) at91_read_msg(dev, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* reactivate mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (mb == get_mb_rx_low_last(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* all lower mailboxed, if just finished it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) at91_activate_rx_low(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else if (mb > get_mb_rx_low_last(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* only the mailbox we read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) at91_activate_rx_mb(priv, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) received++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) quota--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* upper group completed, look again in lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (priv->rx_next > get_mb_rx_low_last(priv) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mb > get_mb_rx_last(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) priv->rx_next = get_mb_rx_first(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (quota > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void at91_poll_err_frame(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct can_frame *cf, u32 reg_sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (reg_sr & AT91_IRQ_CERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) netdev_dbg(dev, "CERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Stuffing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (reg_sr & AT91_IRQ_SERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) netdev_dbg(dev, "SERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) cf->data[2] |= CAN_ERR_PROT_STUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Acknowledgement Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (reg_sr & AT91_IRQ_AERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) netdev_dbg(dev, "AERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) cf->can_id |= CAN_ERR_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Form error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (reg_sr & AT91_IRQ_FERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) netdev_dbg(dev, "FERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cf->data[2] |= CAN_ERR_PROT_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Bit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (reg_sr & AT91_IRQ_BERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) netdev_dbg(dev, "BERR irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) priv->can.can_stats.bus_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) cf->data[2] |= CAN_ERR_PROT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (quota == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) at91_poll_err_frame(dev, cf, reg_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev->stats.rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int at91_poll(struct napi_struct *napi, int quota)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct net_device *dev = napi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) const struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 reg_sr = at91_read(priv, AT91_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (reg_sr & get_irq_mb_rx(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) work_done += at91_poll_rx(dev, quota - work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * The error bits are clear on read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * so use saved value from irq handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) reg_sr |= priv->reg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (reg_sr & AT91_IRQ_ERR_FRAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) work_done += at91_poll_err(dev, quota - work_done, reg_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (work_done < quota) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* enable IRQs for frame errors and all mailboxes >= rx_next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 reg_ier = AT91_IRQ_ERR_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) napi_complete_done(napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) at91_write(priv, AT91_IER, reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * theory of operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * priv->tx_echo holds the number of the oldest can_frame put for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * transmission into the hardware, but not yet ACKed by the CAN tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * complete IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * We iterate from priv->tx_echo to priv->tx_next and check if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * packet has been transmitted, echo it back to the CAN framework. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * we discover a not yet transmitted package, stop looking for more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 reg_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned int mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* masking of reg_sr not needed, already done by at91_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mb = get_tx_echo_mb(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* no event in mailbox? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!(reg_sr & (1 << mb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Disable irq for this TX mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) at91_write(priv, AT91_IDR, 1 << mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * only echo if mailbox signals us a transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * complete (MSR_MRDY). Otherwise it's a tansfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * abort. "can_bus_off()" takes care about the skbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * parked in the echo queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) reg_msr = at91_read(priv, AT91_MSR(mb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (likely(reg_msr & AT91_MSR_MRDY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ~reg_msr & AT91_MSR_MABT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) can_led_event(dev, CAN_LED_EVENT_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * restart queue if we don't have a wrap around but restart if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * we get a TX int for the last can frame directly before a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * wrap around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if ((priv->tx_next & get_next_mask(priv)) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) (priv->tx_echo & get_next_mask(priv)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void at91_irq_err_state(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct can_frame *cf, enum can_state new_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 reg_idr = 0, reg_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct can_berr_counter bec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) at91_get_berr_counter(dev, &bec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) switch (priv->can.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case CAN_STATE_ERROR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * from: ERROR_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * => : there was a warning int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (new_state >= CAN_STATE_ERROR_WARNING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) new_state <= CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) netdev_dbg(dev, "Error Warning IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) priv->can.can_stats.error_warning++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) cf->data[1] = (bec.txerr > bec.rxerr) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) CAN_ERR_CRTL_TX_WARNING :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) CAN_ERR_CRTL_RX_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case CAN_STATE_ERROR_WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * from: ERROR_ACTIVE, ERROR_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * to : ERROR_PASSIVE, BUS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * => : error passive int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (new_state >= CAN_STATE_ERROR_PASSIVE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) new_state <= CAN_STATE_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) netdev_dbg(dev, "Error Passive IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) priv->can.can_stats.error_passive++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cf->can_id |= CAN_ERR_CRTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) cf->data[1] = (bec.txerr > bec.rxerr) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) CAN_ERR_CRTL_TX_PASSIVE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) CAN_ERR_CRTL_RX_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case CAN_STATE_BUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * from: BUS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (new_state <= CAN_STATE_ERROR_PASSIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) cf->can_id |= CAN_ERR_RESTARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) netdev_dbg(dev, "restarted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) priv->can.can_stats.restarts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* process state changes depending on the new state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) switch (new_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case CAN_STATE_ERROR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * actually we want to enable AT91_IRQ_WARN here, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * it screws up the system under certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * circumstances. so just enable AT91_IRQ_ERRP, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * the "fallthrough"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) netdev_dbg(dev, "Error Active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cf->can_id |= CAN_ERR_PROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cf->data[2] = CAN_ERR_PROT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case CAN_STATE_ERROR_WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) reg_ier = AT91_IRQ_ERRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case CAN_STATE_ERROR_PASSIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) reg_ier = AT91_IRQ_BOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case CAN_STATE_BUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) AT91_IRQ_WARN | AT91_IRQ_BOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) reg_ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) cf->can_id |= CAN_ERR_BUSOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) netdev_dbg(dev, "bus-off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) priv->can.can_stats.bus_off++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* turn off chip, if restart is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!priv->can.restart_ms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) at91_chip_stop(dev, CAN_STATE_BUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) at91_write(priv, AT91_IDR, reg_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) at91_write(priv, AT91_IER, reg_ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int at91_get_state_by_bec(const struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) enum can_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct can_berr_counter bec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) err = at91_get_berr_counter(dev, &bec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (bec.txerr < 96 && bec.rxerr < 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) *state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) else if (bec.txerr < 128 && bec.rxerr < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) *state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) else if (bec.txerr < 256 && bec.rxerr < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) *state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static void at91_irq_err(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct can_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) enum can_state new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 reg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (at91_is_sam9263(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) reg_sr = at91_read(priv, AT91_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* we need to look at the unmasked reg_sr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (unlikely(reg_sr & AT91_IRQ_BOFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) new_state = CAN_STATE_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) else if (unlikely(reg_sr & AT91_IRQ_ERRP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) new_state = CAN_STATE_ERROR_PASSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) else if (unlikely(reg_sr & AT91_IRQ_WARN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) new_state = CAN_STATE_ERROR_WARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) else if (likely(reg_sr & AT91_IRQ_ERRA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) new_state = CAN_STATE_ERROR_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) netdev_err(dev, "BUG! hardware in undefined state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) err = at91_get_state_by_bec(dev, &new_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* state hasn't changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (likely(new_state == priv->can.state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) skb = alloc_can_err_skb(dev, &cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) at91_irq_err_state(dev, cf, new_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dev->stats.rx_bytes += cf->can_dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) priv->can.state = new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static irqreturn_t at91_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) irqreturn_t handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 reg_sr, reg_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) reg_sr = at91_read(priv, AT91_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) reg_imr = at91_read(priv, AT91_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Ignore masked interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) reg_sr &= reg_imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!reg_sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Receive or error interrupt? -> napi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * The error bits are clear on read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * save for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) priv->reg_sr = reg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) at91_write(priv, AT91_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* Transmission complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (reg_sr & get_irq_mb_tx(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) at91_irq_tx(dev, reg_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) at91_irq_err(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int at91_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* check or determine and set bittime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) err = open_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* register interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev->name, dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto out_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) can_led_event(dev, CAN_LED_EVENT_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* start chip and queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) at91_chip_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) out_close:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * stop CAN bus activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int at91_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) at91_chip_stop(dev, CAN_STATE_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) close_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) can_led_event(dev, CAN_LED_EVENT_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int at91_set_mode(struct net_device *dev, enum can_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case CAN_MODE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) at91_chip_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const struct net_device_ops at91_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .ndo_open = at91_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .ndo_stop = at91_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .ndo_start_xmit = at91_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .ndo_change_mtu = can_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct at91_priv *priv = netdev_priv(to_net_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (priv->mb0_id & CAN_EFF_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct net_device *ndev = to_net_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct at91_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) unsigned long can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ndev->flags & IFF_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) err = kstrtoul(buf, 0, &can_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (can_id & CAN_EFF_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) can_id &= CAN_SFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) priv->mb0_id = can_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static DEVICE_ATTR(mb0_id, 0644, at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static struct attribute *at91_sysfs_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &dev_attr_mb0_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const struct attribute_group at91_sysfs_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .attrs = at91_sysfs_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const struct of_device_id at91_can_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .compatible = "atmel,at91sam9x5-can",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .data = &at91_at91sam9x5_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .compatible = "atmel,at91sam9263-can",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .data = &at91_at91sam9263_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) MODULE_DEVICE_TABLE(of, at91_can_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) match = of_match_node(at91_can_dt_ids, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dev_err(&pdev->dev, "no matching node found in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return (const struct at91_devtype_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return (const struct at91_devtype_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int at91_can_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) const struct at91_devtype_data *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct at91_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) devtype_data = at91_can_get_driver_data(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!devtype_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(&pdev->dev, "no driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) clk = clk_get(&pdev->dev, "can_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(&pdev->dev, "no clock defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!res || irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto exit_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!request_mem_region(res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) goto exit_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) addr = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) goto exit_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) dev = alloc_candev(sizeof(struct at91_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) 1 << devtype_data->tx_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) goto exit_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev->netdev_ops = &at91_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev->flags |= IFF_ECHO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) priv->can.clock.freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) priv->can.bittiming_const = &at91_bittiming_const;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) priv->can.do_set_mode = at91_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) priv->can.do_get_berr_counter = at91_get_berr_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) CAN_CTRLMODE_LISTENONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) priv->reg_base = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) priv->devtype_data = *devtype_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) priv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) priv->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) priv->mb0_id = 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (at91_is_sam9263(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev->sysfs_groups[0] = &at91_sysfs_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) err = register_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_err(&pdev->dev, "registering netdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) devm_can_led_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) priv->reg_base, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) exit_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) exit_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) exit_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) exit_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static int at91_can_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct at91_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) iounmap(priv->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) free_candev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const struct platform_device_id at91_can_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .name = "at91sam9x5_can",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .name = "at91_can",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) MODULE_DEVICE_TABLE(platform, at91_can_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static struct platform_driver at91_can_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .probe = at91_can_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .remove = at91_can_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .of_match_table = of_match_ptr(at91_can_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .id_table = at91_can_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) module_platform_driver(at91_can_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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