^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MMIO register bitfield-controlled multiplexer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mux/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int mux_mmio_set(struct mux_control *mux, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct regmap_field **fields = mux_chip_priv(mux->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return regmap_field_write(fields[mux_control_get_index(mux)], state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct mux_control_ops mux_mmio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .set = mux_mmio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct of_device_id mux_mmio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .compatible = "mmio-mux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { .compatible = "reg-mux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_DEVICE_TABLE(of, mux_mmio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int mux_mmio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct regmap_field **fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct mux_chip *mux_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int num_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (of_device_is_compatible(np, "mmio-mux"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) regmap = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap = dev_get_regmap(dev->parent, NULL) ?: ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dev_err(dev, "failed to get regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = of_property_count_u32_elems(np, "mux-reg-masks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret == 0 || ret % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev_err(dev, "mux-reg-masks property missing or invalid: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) num_fields = ret / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mux_chip = devm_mux_chip_alloc(dev, num_fields, num_fields *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sizeof(*fields));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (IS_ERR(mux_chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return PTR_ERR(mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) fields = mux_chip_priv(mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for (i = 0; i < num_fields; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mux_control *mux = &mux_chip->mux[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct reg_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) s32 idle_state = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = of_property_read_u32_index(np, "mux-reg-masks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 2 * i, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = of_property_read_u32_index(np, "mux-reg-masks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 2 * i + 1, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) field.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) field.msb = fls(mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) field.lsb = ffs(mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (mask != GENMASK(field.msb, field.lsb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(dev, "bitfield %d: invalid mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) i, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) fields[i] = devm_regmap_field_alloc(dev, regmap, field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(fields[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = PTR_ERR(fields[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(dev, "bitfield %d: failed allocate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bits = 1 + field.msb - field.lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mux->states = 1 << bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) of_property_read_u32_index(np, "idle-states", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (u32 *)&idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (idle_state != MUX_IDLE_AS_IS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (idle_state < 0 || idle_state >= mux->states) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(dev, "bitfield: %d: out of range idle state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) i, idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mux->idle_state = idle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mux_chip->ops = &mux_mmio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return devm_mux_chip_register(dev, mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct platform_driver mux_mmio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "mmio-mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .of_match_table = of_match_ptr(mux_mmio_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .probe = mux_mmio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) module_platform_driver(mux_mmio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MODULE_DESCRIPTION("MMIO register bitfield-controlled multiplexer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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