^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADGS1408/ADGS1409 SPI MUX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mux/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ADGS1408_SW_DATA (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ADGS1408_REG_READ(reg) ((reg) | 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADGS1408_DISABLE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADGS1408_MUX(state) (((state) << 1) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum adgs1408_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ADGS1408 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ADGS1409,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int adgs1408_spi_reg_write(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 reg_addr, u8 reg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 tx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) tx_buf[0] = reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) tx_buf[1] = reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return spi_write_then_read(spi, tx_buf, sizeof(tx_buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int adgs1408_set(struct mux_control *mux, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct spi_device *spi = to_spi_device(mux->chip->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (state == MUX_IDLE_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) reg = ADGS1408_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) reg = ADGS1408_MUX(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct mux_control_ops adgs1408_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .set = adgs1408_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int adgs1408_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum adgs1408_chip_id chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mux_chip *mux_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mux_control *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) s32 idle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) chip_id = (enum adgs1408_chip_id)device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) chip_id = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mux_chip = devm_mux_chip_alloc(dev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (IS_ERR(mux_chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return PTR_ERR(mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mux_chip->ops = &adgs1408_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, ADGS1408_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = device_property_read_u32(dev, "idle-state", (u32 *)&idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) idle_state = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mux = mux_chip->mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (chip_id == ADGS1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mux->states = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mux->states = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (idle_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case MUX_IDLE_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case MUX_IDLE_AS_IS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 0 ... 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* adgs1409 supports only 4 states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (idle_state < mux->states) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mux->idle_state = idle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(dev, "invalid idle-state %d\n", idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return devm_mux_chip_register(dev, mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct spi_device_id adgs1408_spi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { "adgs1408", ADGS1408 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "adgs1409", ADGS1409 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DEVICE_TABLE(spi, adgs1408_spi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct of_device_id adgs1408_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .compatible = "adi,adgs1408", .data = (void *)ADGS1408, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .compatible = "adi,adgs1409", .data = (void *)ADGS1409, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_DEVICE_TABLE(of, adgs1408_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct spi_driver adgs1408_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .name = "adgs1408",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .of_match_table = adgs1408_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .probe = adgs1408_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .id_table = adgs1408_spi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) module_spi_driver(adgs1408_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MODULE_AUTHOR("Mircea Caprioru <mircea.caprioru@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MODULE_DESCRIPTION("Analog Devices ADGS1408 MUX driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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