^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Multiplexer driver for Analog Devices ADG792A/G Triple 4:1 mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Axentia Technologies AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Peter Rosin <peda@axentia.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mux/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ADG792A_LDSW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADG792A_RESETB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADG792A_DISABLE(mux) (0x50 | (mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADG792A_DISABLE_ALL (0x5f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADG792A_MUX(mux, state) (0xc0 | (((mux) + 1) << 2) | (state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADG792A_MUX_ALL(state) (0xc0 | (state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int adg792a_write_cmd(struct i2c_client *i2c, u8 cmd, int reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 data = ADG792A_RESETB | ADG792A_LDSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* ADG792A_RESETB is active low, the chip resets when it is zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) data &= ~ADG792A_RESETB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return i2c_smbus_write_byte_data(i2c, cmd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int adg792a_set(struct mux_control *mux, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct i2c_client *i2c = to_i2c_client(mux->chip->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (mux->chip->controllers == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* parallel mux controller operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (state == MUX_IDLE_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) cmd = ADG792A_DISABLE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cmd = ADG792A_MUX_ALL(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int controller = mux_control_get_index(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (state == MUX_IDLE_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cmd = ADG792A_DISABLE(controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) cmd = ADG792A_MUX(controller, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return adg792a_write_cmd(i2c, cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct mux_control_ops adg792a_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .set = adg792a_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int adg792a_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mux_chip *mux_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) s32 idle_state[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = device_property_read_u32(dev, "#mux-control-cells", &cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (cells >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mux_chip = devm_mux_chip_alloc(dev, cells ? 3 : 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (IS_ERR(mux_chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PTR_ERR(mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mux_chip->ops = &adg792a_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = adg792a_write_cmd(i2c, ADG792A_DISABLE_ALL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = device_property_read_u32_array(dev, "idle-state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (u32 *)idle_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mux_chip->controllers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) idle_state[0] = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) idle_state[1] = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) idle_state[2] = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < mux_chip->controllers; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct mux_control *mux = &mux_chip->mux[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mux->states = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (idle_state[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case MUX_IDLE_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case MUX_IDLE_AS_IS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 0 ... 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mux->idle_state = idle_state[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_err(dev, "invalid idle-state %d\n", idle_state[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = devm_mux_chip_register(dev, mux_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (cells)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_info(dev, "3x single pole quadruple throw muxes registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_info(dev, "triple pole quadruple throw mux registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct i2c_device_id adg792a_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .name = "adg792a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .name = "adg792g", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DEVICE_TABLE(i2c, adg792a_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct of_device_id adg792a_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .compatible = "adi,adg792a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .compatible = "adi,adg792g", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODULE_DEVICE_TABLE(of, adg792a_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct i2c_driver adg792a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "adg792a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .of_match_table = of_match_ptr(adg792a_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .probe_new = adg792a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .id_table = adg792a_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) module_i2c_driver(adg792a_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_DESCRIPTION("Analog Devices ADG792A/G Triple 4:1 mux driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MODULE_AUTHOR("Peter Rosin <peda@axentia.se>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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