^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005, Intec Automation Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014, Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mtd/spi-nor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) w25q256_post_bfpt_fixups(struct spi_nor *nor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) const struct sfdp_parameter_header *bfpt_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) const struct sfdp_bfpt *bfpt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct spi_nor_flash_parameter *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * W25Q256JV supports 4B opcodes but W25Q256FV does not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Unfortunately, Winbond has re-used the same JEDEC ID for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * variants which prevents us from defining a new entry in the parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * To differentiate between W25Q256JV and W25Q256FV check SFDP header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * version: only JV has JESD216A compliant structure (version 5).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (bfpt_header->major == SFDP_JESD216_MAJOR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bfpt_header->minor == SFDP_JESD216A_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) nor->flags |= SNOR_F_4B_OPCODES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct spi_nor_fixups w25q256_fixups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .post_bfpt = w25q256_post_bfpt_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct flash_info winbond_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SECT_4K | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "w25q64jvm", INFO(0xef7017, 0, 64 * 1024, 128, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .fixups = &w25q256_fixups },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @nor: pointer to 'struct spi_nor'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * address mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Return: 0 on success, -errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = spi_nor_set_4byte_addr_mode(nor, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret || enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Register to be set to 1, so all 3-byte-address reads come from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * second 16M. We must clear the register to enable normal behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = spi_nor_write_enable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = spi_nor_write_ear(nor, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return spi_nor_write_disable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void winbond_default_init(struct spi_nor *nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct spi_nor_fixups winbond_fixups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .default_init = winbond_default_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct spi_nor_manufacturer spi_nor_winbond = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "winbond",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .parts = winbond_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .nparts = ARRAY_SIZE(winbond_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .fixups = &winbond_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags