^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005, Intec Automation Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014, Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mtd/spi-nor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static const struct flash_info sst_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* SST -- large erase sizes are "overlays", "sectors" are 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SECT_4K | SPI_NOR_4BIT_BP) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SECT_4K | SST_WRITE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SECT_4K | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SECT_4K | SPI_NOR_DUAL_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SECT_4K | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) size_t *retlen, const u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct spi_nor *nor = mtd_to_spi_nor(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) size_t actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = spi_nor_lock_and_prep(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = spi_nor_write_enable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) nor->sst_write_second = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Start write from odd address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (to % 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nor->program_opcode = SPINOR_OP_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* write one byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = spi_nor_write_data(nor, to, 1, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = spi_nor_wait_till_ready(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) to++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) actual++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Write out most of the data here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (; actual < len - 1; actual += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) nor->program_opcode = SPINOR_OP_AAI_WP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* write two bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = spi_nor_write_data(nor, to, 2, buf + actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = spi_nor_wait_till_ready(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) to += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) nor->sst_write_second = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) nor->sst_write_second = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = spi_nor_write_disable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = spi_nor_wait_till_ready(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Write out trailing byte if it exists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (actual != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = spi_nor_write_enable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) nor->program_opcode = SPINOR_OP_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = spi_nor_write_data(nor, to, 1, buf + actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = spi_nor_wait_till_ready(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) actual += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = spi_nor_write_disable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *retlen += actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spi_nor_unlock_and_unprep(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void sst_default_init(struct spi_nor *nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) nor->flags |= SNOR_F_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void sst_post_sfdp_fixups(struct spi_nor *nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (nor->info->flags & SST_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) nor->mtd._write = sst_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct spi_nor_fixups sst_fixups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .default_init = sst_default_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .post_sfdp = sst_post_sfdp_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct spi_nor_manufacturer spi_nor_sst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "sst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .parts = sst_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .nparts = ARRAY_SIZE(sst_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .fixups = &sst_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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