^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mtd/spi-nor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const struct flash_info puya_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) { "PY25Q128HA", INFO(0x852018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) { "P25Q64H", INFO(0x856017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) { "P25Q128H", INFO(0x856018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) const struct spi_nor_manufacturer spi_nor_puya = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .name = "puya",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .parts = puya_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .nparts = ARRAY_SIZE(puya_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };