^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005, Intec Automation Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014, Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mtd/spi-nor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static const struct flash_info micron_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct flash_info st_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SECT_4K | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SECT_4K | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SECT_4K | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NO_CHIP_ERASE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NO_CHIP_ERASE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) NO_CHIP_ERASE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * flashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @nor: pointer to 'struct spi_nor'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * address mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Return: 0 on success, -errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = spi_nor_write_enable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = spi_nor_set_4byte_addr_mode(nor, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return spi_nor_write_disable(nor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void micron_st_default_init(struct spi_nor *nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) nor->flags |= SNOR_F_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) nor->flags &= ~SNOR_F_HAS_16BIT_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) nor->params->quad_enable = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct spi_nor_fixups micron_st_fixups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .default_init = micron_st_default_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct spi_nor_manufacturer spi_nor_micron = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "micron",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .parts = micron_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .nparts = ARRAY_SIZE(micron_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .fixups = µn_st_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct spi_nor_manufacturer spi_nor_st = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "st",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .parts = st_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .nparts = ARRAY_SIZE(st_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .fixups = µn_st_fixups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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