^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005, Intec Automation Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014, Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mtd/spi-nor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static void gd25q256_default_init(struct spi_nor *nor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Some manufacturer like GigaDevice may use different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * bit to set QE on different memories, so the MFR can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * indicate the quad_enable method for this case, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to set it in the default_init fixup hook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct spi_nor_fixups gd25q256_fixups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .default_init = gd25q256_default_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct flash_info gigadevice_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .fixups = &gd25q256_fixups },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .fixups = &gd25q256_fixups },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "gd25lq255", INFO(0xc86019, 0, 64 * 1024, 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { "gd25lb512m", INFO(0xc8671a, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { "gd25b512m", INFO(0xc8471a, 0, 64 * 1024, 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct spi_nor_manufacturer spi_nor_gigadevice = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = "gigadevice",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .parts = gigadevice_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .nparts = ARRAY_SIZE(gigadevice_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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