Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2020 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Dingqiang Lin <jon.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mtd/spinand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SPINAND_MFR_XTX			0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static SPINAND_OP_VARIANTS(read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static SPINAND_OP_VARIANTS(write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static SPINAND_OP_VARIANTS(update_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	region->offset = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	region->length = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	region->length = mtd->oobsize - 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.ecc = xt26g0xa_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.free = xt26g0xa_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int xt26g01b_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int xt26g01b_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	region->length = mtd->oobsize - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct mtd_ooblayout_ops xt26g01b_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.ecc = xt26g01b_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.free = xt26g01b_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int xt26g02b_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (section > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	region->offset = (16 * section) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	region->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int xt26g02b_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (section > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	region->offset = (16 * section) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	region->length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct mtd_ooblayout_ops xt26g02b_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.ecc = xt26g02b_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.free = xt26g02b_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int xt26g01c_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	region->offset = mtd->oobsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	region->length = mtd->oobsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int xt26g01c_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	region->length = mtd->oobsize / 2 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct mtd_ooblayout_ops xt26g01c_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.ecc = xt26g01c_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.free = xt26g01c_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * ecc bits: 0xC0[2,5]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * [0x0000], No bit errors were detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * [0x0001, 0x0111], Bit errors were detected and corrected. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *	reach Flipping Bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * [0x1000], Multiple bit errors were detected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *	not corrected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * [0x1100], Bit error count equals the bit flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *	detectionthreshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * else, reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				   u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u8 eccsr = (status & GENMASK(5, 2)) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (eccsr <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return eccsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	else if (eccsr == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * ecc bits: 0xC0[4,6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * [0x0], No bit errors were detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * [0x001, 0x011], Bit errors were detected and corrected. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  *	reach Flipping Bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * [0x100], Bit error count equals the bit flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *	detectionthreshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * [0x101, 0x110], Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * [0x111], Multiple bit errors were detected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *	not corrected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int xt26g02b_ecc_get_status(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				   u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u8 eccsr = (status & GENMASK(6, 4)) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (eccsr <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return eccsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * ecc bits: 0xC0[4,7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * [0b0000], No bit errors were detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *	reach Flipping Bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * [0b1000], 8 Bit errors were detected and corrected. Bit error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *	equals the bit flip detectionthreshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * others, Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int xt26g01c_ecc_get_status(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				   u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u8 eccsr = (status & GENMASK(7, 4)) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (eccsr <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return eccsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct spinand_info xtx_spinand_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	SPINAND_INFO("XT26G01A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		     SPINAND_ECCINFO(&xt26g0xa_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				     xt26g0xa_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	SPINAND_INFO("XT26G02A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		     SPINAND_ECCINFO(&xt26g0xa_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				     xt26g0xa_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	SPINAND_INFO("XT26G04A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		     NAND_MEMORG(1, 2048, 64, 128, 2048, 80, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		     SPINAND_ECCINFO(&xt26g0xa_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				     xt26g0xa_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	SPINAND_INFO("XT26G01B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		     SPINAND_ECCINFO(&xt26g01b_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				     xt26g0xa_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	SPINAND_INFO("XT26G02B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		     NAND_ECCREQ(4, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		     SPINAND_ECCINFO(&xt26g02b_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				     xt26g02b_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	SPINAND_INFO("XT26G01C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		     SPINAND_ECCINFO(&xt26g01c_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				     xt26g01c_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	SPINAND_INFO("XT26G02C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		     SPINAND_ECCINFO(&xt26g0xa_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				     xt26g01c_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	SPINAND_INFO("XT26G04C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 80, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		     SPINAND_ECCINFO(&xt26g01c_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				     xt26g01c_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	SPINAND_INFO("XT26G11C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		     SPINAND_HAS_QE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		     SPINAND_ECCINFO(&xt26g01c_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				     xt26g01c_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const struct spinand_manufacturer xtx_spinand_manufacturer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.id = SPINAND_MFR_XTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.name = "xtx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.chips = xtx_spinand_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.nchips = ARRAY_SIZE(xtx_spinand_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.ops = &xtx_spinand_manuf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };