Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 exceet electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Frieder Schrempf <frieder.schrempf@exceet.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Boris Brezillon <boris.brezillon@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mtd/spinand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define SPINAND_MFR_WINBOND		0xEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define WINBOND_CFG_BUF_READ		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define WINBOND_STATUS_ECC_HAS_BITFLIPS_T	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static SPINAND_OP_VARIANTS(read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static SPINAND_OP_VARIANTS(write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static SPINAND_OP_VARIANTS(update_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (section > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	region->offset = (16 * section) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	region->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (section > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	region->offset = (16 * section) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	region->length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.ecc = w25m02gv_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.free = w25m02gv_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int w25m02gv_select_target(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				  unsigned int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 					  SPI_MEM_OP_NO_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					  SPI_MEM_OP_NO_DUMMY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					  SPI_MEM_OP_DATA_OUT(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 							spinand->scratchbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 							1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	*spinand->scratchbuf = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return spi_mem_exec_op(spinand->spimem, &op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	region->offset = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	region->length = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* Reserve 2 bytes for the BBM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	region->length = 62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.ecc = w25n02kv_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.free = w25n02kv_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				   u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct nand_device *nand = spinand_to_nand(spinand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	switch (status & STATUS_ECC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case STATUS_ECC_NO_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case STATUS_ECC_UNCOR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case STATUS_ECC_HAS_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return nanddev_get_ecc_requirements(nand)->strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct spinand_info winbond_spinand_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	SPINAND_INFO("W25M02GV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		     NAND_ECCREQ(1, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	SPINAND_INFO("W25N512GV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		     NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		     NAND_ECCREQ(1, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	SPINAND_INFO("W25N01GV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		     NAND_ECCREQ(1, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	SPINAND_INFO("W25N02KV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		     SPINAND_ECCINFO(&w25n02kv_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				     w25n02kv_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	SPINAND_INFO("W25N04KV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		     NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		     SPINAND_ECCINFO(&w25n02kv_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				     w25n02kv_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	SPINAND_INFO("W25N01GW",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		     NAND_ECCREQ(1, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		     SPINAND_SELECT_TARGET(w25m02gv_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	SPINAND_INFO("W25N02KW",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		     SPINAND_ECCINFO(&w25n02kv_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				     w25n02kv_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	SPINAND_INFO("W25N01KV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAE, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		     NAND_ECCREQ(4, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					      &write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					      &update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		     SPINAND_ECCINFO(&w25n02kv_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				     w25n02kv_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int winbond_spinand_init(struct spinand_device *spinand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct nand_device *nand = spinand_to_nand(spinand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Make sure all dies are in buffer read mode and not continuous read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	for (i = 0; i < nand->memorg.ntargets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		spinand_select_target(spinand, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				WINBOND_CFG_BUF_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.init = winbond_spinand_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct spinand_manufacturer winbond_spinand_manufacturer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.id = SPINAND_MFR_WINBOND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.name = "Winbond",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.chips = winbond_spinand_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.nchips = ARRAY_SIZE(winbond_spinand_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.ops = &winbond_spinand_manuf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };