Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016-2017 Micron Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Peter Pan <peterpandong@micron.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mtd/spinand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SPINAND_MFR_MICRON		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MICRON_STATUS_ECC_NO_BITFLIPS	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MICRON_STATUS_ECC_1TO3_BITFLIPS	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MICRON_CFG_CR			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * As per datasheet, die selection is done by the 6th bit of Die
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Select Register (Address 0xD0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MICRON_DIE_SELECT_REG	0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MICRON_SELECT_DIE(x)	((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static SPINAND_OP_VARIANTS(x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static SPINAND_OP_VARIANTS(x4_update_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Micron  MT29F2G01AAAED Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static SPINAND_OP_VARIANTS(x4_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			   SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			   SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			   SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			   SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static SPINAND_OP_VARIANTS(x1_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			   SPINAND_PROG_LOAD(true, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static SPINAND_OP_VARIANTS(x1_update_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			   SPINAND_PROG_LOAD(false, 0, NULL, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	region->offset = mtd->oobsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	region->length = mtd->oobsize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Reserve 2 bytes for the BBM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	region->length = (mtd->oobsize / 2) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const struct mtd_ooblayout_ops micron_8_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.ecc = micron_8_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.free = micron_8_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				  struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct spinand_device *spinand = mtd_to_spinand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (section >= spinand->base.memorg.pagesize /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			mtd->ecc_step_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	region->offset = (section * 16) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	region->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int micron_4_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				   struct mtd_oob_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct spinand_device *spinand = mtd_to_spinand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (section >= spinand->base.memorg.pagesize /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			mtd->ecc_step_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (section) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		region->offset = 16 * section;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		region->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		/* section 0 has two bytes reserved for the BBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		region->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		region->length = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct mtd_ooblayout_ops micron_4_ooblayout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.ecc = micron_4_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.free = micron_4_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int micron_select_target(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				unsigned int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 						      spinand->scratchbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (target > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	*spinand->scratchbuf = MICRON_SELECT_DIE(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return spi_mem_exec_op(spinand->spimem, &op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int micron_8_ecc_get_status(struct spinand_device *spinand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				   u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	switch (status & MICRON_STATUS_ECC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case STATUS_ECC_NO_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case STATUS_ECC_UNCOR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case MICRON_STATUS_ECC_1TO3_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	case MICRON_STATUS_ECC_4TO6_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	case MICRON_STATUS_ECC_7TO8_BITFLIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct spinand_info micron_spinand_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* M79A 2Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	SPINAND_INFO("MT29F2G01ABAGD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* M79A 2Gb 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	SPINAND_INFO("MT29F2G01ABBGD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* M78A 1Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	SPINAND_INFO("MT29F1G01ABAFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* M78A 1Gb 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	SPINAND_INFO("MT29F1G01ABAFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* M79A 4Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	SPINAND_INFO("MT29F4G01ADAGD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				     micron_8_ecc_get_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		     SPINAND_SELECT_TARGET(micron_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* M70A 4Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	SPINAND_INFO("MT29F4G01ABAFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		     SPINAND_HAS_CR_FEAT_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* M70A 4Gb 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	SPINAND_INFO("MT29F4G01ABBFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		     SPINAND_HAS_CR_FEAT_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				     micron_8_ecc_get_status)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* M70A 8Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	SPINAND_INFO("MT29F8G01ADAFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		     SPINAND_HAS_CR_FEAT_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				     micron_8_ecc_get_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		     SPINAND_SELECT_TARGET(micron_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* M70A 8Gb 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	SPINAND_INFO("MT29F8G01ADBFD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		     NAND_ECCREQ(8, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		     SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 					      &x4_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					      &x4_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		     SPINAND_HAS_CR_FEAT_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		     SPINAND_ECCINFO(&micron_8_ooblayout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				     micron_8_ecc_get_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		     SPINAND_SELECT_TARGET(micron_select_target)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* M69A 2Gb 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	SPINAND_INFO("MT29F2G01AAAED",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		     NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		     NAND_ECCREQ(4, 512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		     SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					      &x1_write_cache_variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					      &x1_update_cache_variants),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		     0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		     SPINAND_ECCINFO(&micron_4_ooblayout, NULL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int micron_spinand_init(struct spinand_device *spinand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * M70A device series enable Continuous Read feature at Power-up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 * which is not supported. Disable this bit to avoid any possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.init = micron_spinand_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct spinand_manufacturer micron_spinand_manufacturer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.id = SPINAND_MFR_MICRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.name = "Micron",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.chips = micron_spinand_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.nchips = ARRAY_SIZE(micron_spinand_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.ops = &micron_spinand_manuf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };