^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TXx9 NAND flash memory controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright TOSHIBA CORPORATION 2004-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/nand_ecc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/txx9/ndfmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* TXX9 NDFMC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TXX9_NDFDTR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TXX9_NDFMCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TXX9_NDFSR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TXX9_NDFISR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TXX9_NDFIMR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TXX9_NDFSPR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TXX9_NDFRSTR 0x18 /* not TX4939 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* NDFMCR : NDFMC Mode Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TXX9_NDFMCR_WE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TXX9_NDFMCR_ECC_ALL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TXX9_NDFMCR_ECC_RESET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TXX9_NDFMCR_ECC_READ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TXX9_NDFMCR_ECC_ON 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TXX9_NDFMCR_ECC_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TXX9_NDFMCR_CE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TXX9_NDFMCR_ALE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TXX9_NDFMCR_CLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* TX4939 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TXX9_NDFMCR_X16 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TXX9_NDFMCR_DMAREQ_128 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TXX9_NDFMCR_DMAREQ_256 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TXX9_NDFMCR_DMAREQ_512 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TXX9_NDFMCR_CS_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TXX9_NDFMCR_CS(ch) ((ch) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* NDFMCR : NDFMC Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TXX9_NDFSR_BUSY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* TX4939 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TXX9_NDFSR_DMARUN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* NDFMCR : NDFMC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TXX9_NDFRSTR_RST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct txx9ndfmc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct platform_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct nand_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *mtdname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_TXX9NDFMC_DEV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct txx9ndfmc_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned char hold; /* in gbusclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned char spw; /* in gbusclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct nand_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct nand_chip *chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return txx9_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return drvdata->base + (reg << plat->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return __raw_readl(ndregaddr(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void txx9ndfmc_write(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __raw_writel(val, ndregaddr(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static uint8_t txx9ndfmc_read_byte(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return txx9ndfmc_read(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void txx9ndfmc_write_buf(struct nand_chip *chip, const uint8_t *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __raw_writel(*buf++, ndfdtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void txx9ndfmc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *buf++ = __raw_readl(ndfdtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void txx9ndfmc_cmd_ctrl(struct nand_chip *chip, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct platform_device *dev = txx9_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ctrl & NAND_CTRL_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* TXX9_NDFMCR_CE bit is 0:high 1:low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mcr &= ~TXX9_NDFMCR_CS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (cmd != NAND_CMD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* dummy write to update external latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int txx9ndfmc_dev_ready(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int txx9ndfmc_calculate_ecc(struct nand_chip *chip, const uint8_t *dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint8_t *ecc_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int eccbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mcr &= ~TXX9_NDFMCR_ECC_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ecc_code += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int txx9ndfmc_correct_data(struct nand_chip *chip, unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned char *read_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char *calc_ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int eccsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int corrected = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (stat < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) corrected += stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) buf += 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) read_ecc += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) calc_ecc += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return corrected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void txx9ndfmc_enable_hwecc(struct nand_chip *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct platform_device *dev = mtd_to_platdev(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mcr &= ~TXX9_NDFMCR_ECC_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void txx9ndfmc_initialize(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int tmout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* reset NDFMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) txx9ndfmc_write(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) txx9ndfmc_read(dev, TXX9_NDFRSTR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TXX9_NDFRSTR_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) TXX9_NDFRSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (--tmout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(&dev->dev, "reset failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* setup Hold Time, Strobe Pulse Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) txx9ndfmc_write(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int txx9ndfmc_attach_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) chip->ecc.strength = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (mtd->writesize >= 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) chip->ecc.size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) chip->ecc.bytes = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) chip->ecc.size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) chip->ecc.bytes = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chip->ecc.calculate = txx9ndfmc_calculate_ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) chip->ecc.correct = txx9ndfmc_correct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct nand_controller_ops txx9ndfmc_controller_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .attach_chip = txx9ndfmc_attach_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int __init txx9ndfmc_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int hold, spw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct txx9ndfmc_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long gbusclk = plat->gbus_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) drvdata->base = devm_ioremap_resource(&dev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(drvdata->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return PTR_ERR(drvdata->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) hold = plat->hold ?: 20; /* tDH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hold = clamp(hold, 1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) drvdata->hold = hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spw = clamp(spw, 1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) drvdata->spw = spw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (gbusclk + 500000) / 1000000, hold, spw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) nand_controller_init(&drvdata->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) drvdata->controller.ops = &txx9ndfmc_controller_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) platform_set_drvdata(dev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) txx9ndfmc_initialize(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct txx9ndfmc_priv *txx9_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct nand_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!(plat->ch_mask & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!txx9_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chip = &txx9_priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mtd->dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) chip->legacy.read_byte = txx9ndfmc_read_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) chip->legacy.read_buf = txx9ndfmc_read_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) chip->legacy.write_buf = txx9ndfmc_write_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) chip->legacy.dev_ready = txx9ndfmc_dev_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) chip->legacy.chip_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) chip->controller = &drvdata->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) nand_set_controller_data(chip, txx9_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) txx9_priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (plat->ch_mask != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) txx9_priv->cs = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_name(&dev->dev), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) txx9_priv->cs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!txx9_priv->mtdname) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) kfree(txx9_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(&dev->dev, "Unable to allocate MTD name.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (plat->wide_mask & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip->options |= NAND_BUSWIDTH_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (nand_scan(chip, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) kfree(txx9_priv->mtdname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) kfree(txx9_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mtd->name = txx9_priv->mtdname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mtd_device_register(mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) drvdata->mtds[i] = mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int __exit txx9ndfmc_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mtd_info *mtd = drvdata->mtds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct nand_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct txx9ndfmc_priv *txx9_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) txx9_priv = nand_get_controller_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = mtd_device_unregister(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) kfree(txx9_priv->mtdname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) kfree(txx9_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int txx9ndfmc_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (platform_get_drvdata(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) txx9ndfmc_initialize(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define txx9ndfmc_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct platform_driver txx9ndfmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .remove = __exit_p(txx9ndfmc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .resume = txx9ndfmc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = "txx9ndfmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_ALIAS("platform:txx9ndfmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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