^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2009 - Maxim Levitsky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * driver for Ricoh xD readers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* nand interface + ecc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) byte write/read does one cycle on nand data lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) dword write/read does 4 cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) if R852_CTL_ECC_ACCESS is set in R852_CTL, then dword read reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) results of ecc correction, if DMA read was done before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) If write was done two dword reads read generated ecc checksums
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R852_DATALINE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R852_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R852_CTL_COMMAND 0x01 /* send command (#CLE)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R852_CTL_ON 0x04 /* only seem to controls the hd led, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* but has to be set on start...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R852_CTL_RESET 0x08 /* unknown, set only on start once*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R852_CTL_WRITE 0x80 /* set when performing writes (#WP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* card detection status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R852_CARD_STA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R852_CARD_STA_CD 0x01 /* state of #CD line, same as 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R852_CARD_STA_RO 0x02 /* card is readonly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R852_CARD_STA_PRESENT 0x04 /* card is present (#CD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R852_CARD_STA_ABSENT 0x08 /* card is absent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* card detection irq status & enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R852_CARD_IRQ_STA 0x06 /* IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R852_CARD_IRQ_CD 0x01 /* fire when #CD lights, same as 0x04*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R852_CARD_IRQ_REMOVE 0x04 /* detect card removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R852_CARD_IRQ_INSERT 0x08 /* detect card insert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R852_CARD_IRQ_UNK1 0x10 /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R852_CARD_IRQ_GENABLE 0x80 /* general enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R852_CARD_IRQ_MASK 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* hardware enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R852_HW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R852_HW_ENABLED 0x01 /* hw enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R852_HW_UNKNOWN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* dma capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R852_DMA_CAP 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R852_SMBIT 0x20 /* if set with bit #6 or bit #7, then */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* hw is smartmedia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R852_DMA1 0x40 /* if set w/bit #7, dma is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R852_DMA2 0x80 /* if set w/bit #6, dma is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* physical DMA address - 32 bit value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R852_DMA_ADDR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* dma settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R852_DMA_SETTINGS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R852_DMA_READ 0x02 /* 0 = write, 1 = read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* dma IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R852_DMA_IRQ_STA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* dma IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R852_DMA_IRQ_ENABLE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R852_DMA_IRQ_ERROR 0x02 /* error did happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R852_DMA_IRQ_MASK 0x07 /* mask of all IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* ECC syndrome format - read from reg #0 will return two copies of these for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) each half of the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) first byte is error byte location, and second, bit location + flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R852_ECC_ERR_BIT_MSK 0x07 /* error bit location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R852_ECC_CORRECTABLE 0x20 /* correctable error exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R852_ECC_FAIL 0x40 /* non correctable error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R852_DMA_LEN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DMA_INTERNAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DMA_MEMORY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct r852_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct nand_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *mmio; /* mmio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct nand_chip *chip; /* nand chip backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_dev *pci_dev; /* pci backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* dma area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dma_addr_t phys_dma_addr; /* bus address of buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct completion dma_done; /* data transfer done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dma_addr_t phys_bounce_buffer; /* bus address of bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t *bounce_buffer; /* virtual address of bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int dma_dir; /* 1 = read, 0 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int dma_stage; /* 0 - idle, 1 - first step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 2 - second step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int dma_state; /* 0 = internal, 1 = memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int dma_error; /* dma errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int dma_usable; /* is it possible to use dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* card status area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct delayed_work card_detect_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct workqueue_struct *card_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int card_registered; /* card registered with mtd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int card_detected; /* card detected in slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int card_unstable; /* whenever the card is inserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) is not known yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int readonly; /* card is readonly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int sm; /* Is card smartmedia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* interrupt handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spinlock_t irqlock; /* IRQ protecting lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int irq; /* irq num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void *tmp_buffer; /* temporary buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint8_t ctlreg; /* cached contents of control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define dbg(format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_debug(format "\n", ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define dbg_verbose(format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (debug > 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_debug(format "\n", ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define message(format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_info(format "\n", ## __VA_ARGS__)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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