^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NAND Flash Controller Device Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DENALI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DENALI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEVICE_RESET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEVICE_RESET__BANK(bank) BIT(bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TRANSFER_SPARE_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TRANSFER_SPARE_REG__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LOAD_WAIT_CNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PROGRAM_WAIT_CNT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ERASE_WAIT_CNT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INT_MON_CYCCNT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RB_PIN_ENABLED 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MULTIPLANE_OPERATION 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MULTIPLANE_OPERATION__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MULTIPLANE_READ_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define COPYBACK_DISABLE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define COPYBACK_DISABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CACHE_WRITE_ENABLE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CACHE_WRITE_ENABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CACHE_READ_ENABLE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CACHE_READ_ENABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PREFETCH_MODE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PREFETCH_MODE__PREFETCH_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHIP_ENABLE_DONT_CARE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CHIP_EN_DONT_CARE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ECC_ENABLE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ECC_ENABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GLOBAL_INT_ENABLE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GLOBAL_INT_EN_FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TWHR2_AND_WE_2_RE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TCWAW_AND_ADDR_2_DATA 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RE_2_WE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RE_2_WE__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ACC_CLKS 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ACC_CLKS__VALUE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NUMBER_OF_PLANES 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PAGES_PER_BLOCK 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DEVICE_WIDTH 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DEVICE_WIDTH__VALUE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEVICE_MAIN_AREA_SIZE 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEVICE_SPARE_AREA_SIZE 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TWO_ROW_ADDR_CYCLES 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MULTIPLANE_ADDR_RESTRICT 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ECC_CORRECTION 0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ECC_CORRECTION__VALUE GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define READ_MODE 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define READ_MODE__VALUE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WRITE_MODE 0x1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WRITE_MODE__VALUE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define COPYBACK_MODE 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define COPYBACK_MODE__VALUE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RDWR_EN_LO_CNT 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RDWR_EN_HI_CNT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MAX_RD_DELAY 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAX_RD_DELAY__VALUE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CS_SETUP_CNT 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CS_SETUP_CNT__VALUE GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CS_SETUP_CNT__TWB GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPARE_AREA_SKIP_BYTES 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SPARE_AREA_MARKER 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DEVICES_CONNECTED 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DIE_MASK 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DIE_MASK__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WRITE_PROTECT 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WRITE_PROTECT__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RE_2_RE 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RE_2_RE__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MANUFACTURER_ID 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MANUFACTURER_ID__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DEVICE_ID 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DEVICE_ID__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DEVICE_PARAM_0 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DEVICE_PARAM_1 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DEVICE_PARAM_2 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LOGICAL_PAGE_DATA_SIZE 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LOGICAL_PAGE_SPARE_SIZE 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define REVISION 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REVISION__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ONFI_DEVICE_FEATURES 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ONFI_OPTIONAL_COMMANDS 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ONFI_TIMING_MODE 0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FEATURES 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FEATURES__N_BANKS GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FEATURES__DMA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FEATURES__CMD_DMA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FEATURES__PARTITION BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FEATURES__XDMA_SIDEBAND BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FEATURES__GPREG BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FEATURES__INDEX_ADDR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TRANSFER_MODE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TRANSFER_MODE__VALUE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define INTR_EN(bank) (0x420 + (bank) * 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* bit[1:0] is used differently depending on IP version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define INTR__ECC_ERR BIT(1) /* old IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define INTR__DMA_CMD_COMP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define INTR__TIME_OUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define INTR__PROGRAM_FAIL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define INTR__ERASE_FAIL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define INTR__LOAD_COMP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define INTR__PROGRAM_COMP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define INTR__ERASE_COMP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define INTR__LOCKED_BLK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define INTR__UNSUP_CMD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define INTR__INT_ACT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define INTR__RST_COMP BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define INTR__PIPE_CMD_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define INTR__PAGE_XFER_INC BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define INTR__ERASED_PAGE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ECC_THRESHOLD 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ECC_THRESHOLD__VALUE GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ECC_ERROR_BLOCK_ADDRESS 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ECC_ERROR_PAGE_ADDRESS 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ECC_ERROR_ADDRESS 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ERR_CORRECTION_INFO 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ERR_CORRECTION_INFO__UNCOR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ECC_COR_INFO__UNCOR_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CFG_DATA_BLOCK_SIZE 0x6b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CFG_NUM_DATA_BLOCKS 0x6d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CFG_META_DATA_SIZE 0x6e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DMA_ENABLE 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DMA_ENABLE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IGNORE_ECC_DONE 0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IGNORE_ECC_DONE__FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DMA_INTR 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DMA_INTR_EN 0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DMA_INTR__TARGET_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TARGET_ERR_ADDR_LO 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TARGET_ERR_ADDR_HI 0x750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CHNL_ACTIVE 0x760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CHNL_ACTIVE__CHANNEL0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CHNL_ACTIVE__CHANNEL1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CHNL_ACTIVE__CHANNEL2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CHNL_ACTIVE__CHANNEL3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * struct denali_chip_sel - per-CS data of Denali NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @bank: bank id of the controller this CS is connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @re_2_we: value of timing register RE_2_WE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @acc_clks: value of timing register ACC_CLKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @rdwr_en_hi_cnt: value of timing register RDWR_EN_HI_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @cs_setup_cnt: value of timing register CS_SETUP_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @re_2_re: value of timing register RE_2_RE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct denali_chip_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 hwhr2_and_we_2_re;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 tcwaw_and_addr_2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 re_2_we;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 acc_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 rdwr_en_lo_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 rdwr_en_hi_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 cs_setup_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 re_2_re;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * struct denali_chip - per-chip data of Denali NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @chip: base NAND chip structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @node: node to be used to associate this chip with the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * @nsels: the number of CS lines of this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @sels: the array of per-cs data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct denali_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct nand_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int nsels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct denali_chip_sel sels[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * struct denali_controller - Denali NAND controller data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @controller: base NAND controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @chips: the list of chips attached to this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @clk_rate: frequency of core clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @clk_x_rate: frequency of bus interface clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @reg: base of Register Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @host: base of Host Data/Command interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * @complete: completion used to wait for interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @irq_mask: interrupt bits the controller is waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @irq_status: interrupt bits of events that have happened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @irq_lock: lock to protect @irq_mask and @irq_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @dma_avail: set if DMA engine is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @devs_per_cs: number of devices connected in parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @active_bank: active bank id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @nbanks: the number of banks supported by this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @revision: IP revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @caps: controller capabilities that cannot be detected run-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @ecc_caps: ECC engine capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @host_read: callback for read access of Host Data/Command Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @host_write: callback for write access of Host Data/Command Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @setup_dma: callback for setup of the Data DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct denali_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct nand_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct list_head chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long clk_x_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void __iomem *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bool dma_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int devs_per_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int active_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct nand_ecc_caps *ecc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 (*host_read)(struct denali_controller *denali, u32 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void (*host_write)(struct denali_controller *denali, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int page, bool write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DENALI_CAP_HW_ECC_FIXUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DENALI_CAP_DMA_64BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int denali_calc_ecc_bytes(int step_size, int strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int denali_chip_init(struct denali_controller *denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct denali_chip *dchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int denali_init(struct denali_controller *denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void denali_remove(struct denali_controller *denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif /* __DENALI_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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