^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NAND Flash Controller Device Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2009-2010, Intel Corporation and its suppliers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017-2019 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Reworked by Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "denali.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DENALI_NAND_NAME "denali-nand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* for Indexed Addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DENALI_INDEXED_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DENALI_INDEXED_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DENALI_MAP10 (2 << 26) /* high-level control plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DENALI_MAP11 (3 << 26) /* direct controller access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* MAP11 access cycle type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DENALI_BANK(denali) ((denali)->active_bank << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DENALI_INVALID_BANK -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct denali_chip *to_denali_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return container_of(chip, struct denali_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct denali_controller *to_denali_controller(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return container_of(chip->controller, struct denali_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Direct Addressing - the slave address forms the control information (command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * type, bank, block, and page address). The slave data is the actual data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * be transferred. This mode requires 28 bits of address region allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u32 denali_direct_read(struct denali_controller *denali, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ioread32(denali->host + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void denali_direct_write(struct denali_controller *denali, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) iowrite32(data, denali->host + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Indexed Addressing - address translation module intervenes in passing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * control information. This mode reduces the required address range. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * control information and transferred data are latched by the registers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the translation module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static u32 denali_indexed_read(struct denali_controller *denali, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ioread32(denali->host + DENALI_INDEXED_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void denali_indexed_write(struct denali_controller *denali, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) iowrite32(data, denali->host + DENALI_INDEXED_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void denali_enable_irq(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < denali->nbanks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite32(U32_MAX, denali->reg + INTR_EN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void denali_disable_irq(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 0; i < denali->nbanks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iowrite32(0, denali->reg + INTR_EN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void denali_clear_irq(struct denali_controller *denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int bank, u32 irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* write one to clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void denali_clear_irq_all(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (i = 0; i < denali->nbanks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) denali_clear_irq(denali, i, U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static irqreturn_t denali_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct denali_controller *denali = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spin_lock(&denali->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = 0; i < denali->nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irq_status = ioread32(denali->reg + INTR_STATUS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) denali_clear_irq(denali, i, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (i != denali->active_bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) denali->irq_status |= irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (denali->irq_status & denali->irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) complete(&denali->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock(&denali->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void denali_reset_irq(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_lock_irqsave(&denali->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) denali->irq_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) denali->irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_unlock_irqrestore(&denali->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static u32 denali_wait_for_irq(struct denali_controller *denali, u32 irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_lock_irqsave(&denali->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) irq_status = denali->irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (irq_mask & irq_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* return immediately if the IRQ has already happened. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_unlock_irqrestore(&denali->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) denali->irq_mask = irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reinit_completion(&denali->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_unlock_irqrestore(&denali->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) time_left = wait_for_completion_timeout(&denali->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return denali->irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void denali_select_target(struct nand_chip *chip, int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct denali_chip_sel *sel = &to_denali_chip(chip)->sels[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) denali->active_bank = sel->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) iowrite32(1 << (chip->phys_erase_shift - chip->page_shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) denali->reg + PAGES_PER_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) denali->reg + DEVICE_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iowrite32(chip->options & NAND_ROW_ADDR_3 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0 : TWO_ROW_ADDR_CYCLES__FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) denali->reg + TWO_ROW_ADDR_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) denali->reg + ECC_CORRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (chip->options & NAND_KEEP_TIMINGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* update timing registers unless NAND_KEEP_TIMINGS is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iowrite32(sel->tcwaw_and_addr_2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) denali->reg + TCWAW_AND_ADDR_2_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iowrite32(sel->re_2_we, denali->reg + RE_2_WE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) iowrite32(sel->acc_clks, denali->reg + ACC_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iowrite32(sel->re_2_re, denali->reg + RE_2_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int denali_change_column(struct nand_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void *buf, unsigned int len, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return nand_change_write_column_op(chip, offset, buf, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return nand_change_read_column_op(chip, offset, buf, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int denali_payload_xfer(struct nand_chip *chip, void *buf, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct nand_ecc_ctrl *ecc = &chip->ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int writesize = mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int oob_skip = denali->oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret, i, pos, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; i < ecc->steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pos = i * (ecc->size + ecc->bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) len = ecc->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (pos >= writesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else if (pos + len > writesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* This chunk overwraps the BBM area. Must be split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = denali_change_column(chip, pos, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writesize - pos, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) buf += writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) len -= writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pos = writesize + oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = denali_change_column(chip, pos, buf, len, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int denali_oob_xfer(struct nand_chip *chip, void *buf, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct nand_ecc_ctrl *ecc = &chip->ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int writesize = mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int oobsize = mtd->oobsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int oob_skip = denali->oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret, i, pos, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* BBM at the beginning of the OOB area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = denali_change_column(chip, writesize, buf, oob_skip, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) buf += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (i = 0; i < ecc->steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pos = ecc->size + i * (ecc->size + ecc->bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (i == ecc->steps - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* The last chunk includes OOB free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) len = writesize + oobsize - pos - oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) len = ecc->bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (pos >= writesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else if (pos + len > writesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* This chunk overwraps the BBM area. Must be split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = denali_change_column(chip, pos, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writesize - pos, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) buf += writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) len -= writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pos = writesize + oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = denali_change_column(chip, pos, buf, len, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int denali_read_raw(struct nand_chip *chip, void *buf, void *oob_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!buf && !oob_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = nand_read_page_op(chip, page, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = denali_payload_xfer(chip, buf, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (oob_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = denali_oob_xfer(chip, oob_buf, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int denali_write_raw(struct nand_chip *chip, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const void *oob_buf, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!buf && !oob_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = denali_payload_xfer(chip, (void *)buf, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (oob_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = denali_oob_xfer(chip, (void *)oob_buf, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return nand_prog_page_end_op(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int denali_read_page_raw(struct nand_chip *chip, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return denali_read_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int denali_write_page_raw(struct nand_chip *chip, const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return denali_write_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int denali_read_oob(struct nand_chip *chip, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return denali_read_raw(chip, NULL, chip->oob_poi, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int denali_write_oob(struct nand_chip *chip, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return denali_write_raw(chip, NULL, chip->oob_poi, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int denali_check_erased_page(struct nand_chip *chip, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long uncor_ecc_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int max_bitflips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct nand_ecc_ctrl *ecc = &chip->ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int i, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) for (i = 0; i < ecc->steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!(uncor_ecc_flags & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) stat = nand_check_erased_ecc_chunk(buf, ecc->size, ecc_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ecc->bytes, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ecc->strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (stat < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ecc_stats->failed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ecc_stats->corrected += stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) max_bitflips = max_t(unsigned int, max_bitflips, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) buf += ecc->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ecc_code += ecc->bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return max_bitflips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int denali_hw_ecc_fixup(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long *uncor_ecc_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int bank = denali->active_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 ecc_cor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int max_bitflips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * This flag is set when uncorrectable error occurs at least in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * one ECC sector. We can not know "how many sectors", or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * "which sector(s)". We need erase-page check for all sectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * The register holds the maximum of per-sector corrected bitflips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * This is suitable for the return value of the ->read_page() callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Unfortunately, we can not know the total number of corrected bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * the page. Increase the stats by max_bitflips. (compromised solution)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ecc_stats->corrected += max_bitflips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return max_bitflips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int denali_sw_ecc_fixup(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned long *uncor_ecc_flags, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int ecc_size = chip->ecc.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int bitflips = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int max_bitflips = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 err_addr, err_cor_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int err_byte, err_sector, err_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 err_cor_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int prev_sector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) denali_reset_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) err_cor_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err_cor_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* reset the bitflip counter when crossing ECC sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (err_sector != prev_sector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bitflips = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Check later if this is a real ECC error, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * an erased sector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *uncor_ecc_flags |= BIT(err_sector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else if (err_byte < ecc_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * If err_byte is larger than ecc_size, means error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * happened in OOB, so we ignore it. It's no need for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * us to correct it err_device is represented the NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * error bits are happened in if there are more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * one NAND connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int flips_in_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) offset = (err_sector * ecc_size + err_byte) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) denali->devs_per_cs + err_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* correct the ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) buf[offset] ^= err_cor_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ecc_stats->corrected += flips_in_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bitflips += flips_in_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) max_bitflips = max(max_bitflips, bitflips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) prev_sector = err_sector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Once handle all ECC errors, controller will trigger an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * ECC_TRANSACTION_DONE interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return max_bitflips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void denali_setup_dma64(struct denali_controller *denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dma_addr_t dma_addr, int page, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const int page_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* DMA is a three step process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * 1. setup transfer type, interrupt when complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * burst len = 64 bytes, the number of pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) denali->host_write(denali, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x01002000 | (64 << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (write ? BIT(8) : 0) | page_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* 2. set memory low address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) denali->host_write(denali, mode, lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* 3. set memory high address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) denali->host_write(denali, mode, upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void denali_setup_dma32(struct denali_controller *denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dma_addr_t dma_addr, int page, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const int page_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mode = DENALI_MAP10 | DENALI_BANK(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* DMA is a four step process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* 1. setup transfer type and # of pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) denali->host_write(denali, mode | page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x2000 | (write ? BIT(8) : 0) | page_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* 2. set memory high address bits 23:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* 3. set memory low address bits 23:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* 4. interrupt when complete, burst len = 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) denali->host_write(denali, mode | 0x14000, 0x2400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int denali_pio_read(struct denali_controller *denali, u32 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) size_t size, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 irq_status, ecc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ecc_err_mask = INTR__ECC_UNCOR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ecc_err_mask = INTR__ECC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) denali_reset_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) for (i = 0; i < size / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) buf[i] = denali->host_read(denali, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!(irq_status & INTR__PAGE_XFER_INC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (irq_status & INTR__ERASED_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) memset(buf, 0xff, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return irq_status & ecc_err_mask ? -EBADMSG : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int denali_pio_write(struct denali_controller *denali, const u32 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) size_t size, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) denali_reset_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for (i = 0; i < size / 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) denali->host_write(denali, addr, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) irq_status = denali_wait_for_irq(denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) INTR__PROGRAM_COMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) INTR__PROGRAM_FAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!(irq_status & INTR__PROGRAM_COMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int denali_pio_xfer(struct denali_controller *denali, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) size_t size, int page, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return denali_pio_write(denali, buf, size, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return denali_pio_read(denali, buf, size, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int denali_dma_xfer(struct denali_controller *denali, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) size_t size, int page, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 irq_mask, irq_status, ecc_err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dma_addr = dma_map_single(denali->dev, buf, size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (dma_mapping_error(denali->dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return denali_pio_xfer(denali, buf, size, page, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * when the page program is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ecc_err_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) irq_mask = INTR__DMA_CMD_COMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ecc_err_mask = INTR__ECC_UNCOR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) irq_mask = INTR__DMA_CMD_COMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ecc_err_mask = INTR__ECC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * The ->setup_dma() hook kicks DMA by using the data/command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * interface, which belongs to a different AXI port from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * register interface. Read back the register to avoid a race.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ioread32(denali->reg + DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) denali_reset_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) denali->setup_dma(denali, dma_addr, page, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) irq_status = denali_wait_for_irq(denali, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!(irq_status & INTR__DMA_CMD_COMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else if (irq_status & ecc_err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) iowrite32(0, denali->reg + DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dma_unmap_single(denali->dev, dma_addr, size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (irq_status & INTR__ERASED_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) memset(buf, 0xff, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int denali_page_xfer(struct nand_chip *chip, void *buf, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int page, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) denali_select_target(chip, chip->cur_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (denali->dma_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return denali_dma_xfer(denali, buf, size, page, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return denali_pio_xfer(denali, buf, size, page, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int denali_read_page(struct nand_chip *chip, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long uncor_ecc_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = denali_page_xfer(chip, buf, mtd->writesize, page, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret && ret != -EBADMSG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) stat = denali_hw_ecc_fixup(chip, &uncor_ecc_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) else if (ret == -EBADMSG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) stat = denali_sw_ecc_fixup(chip, &uncor_ecc_flags, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (stat < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (uncor_ecc_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = denali_read_oob(chip, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) stat = denali_check_erased_page(chip, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) uncor_ecc_flags, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int denali_write_page(struct nand_chip *chip, const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return denali_page_xfer(chip, (void *)buf, mtd->writesize, page, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int denali_setup_interface(struct nand_chip *chip, int chipnr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) const struct nand_interface_config *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const unsigned int data_setup_on_host = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct denali_chip_sel *sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const struct nand_sdr_timings *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned long t_x, mult_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int addr_2_data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) timings = nand_get_sdr_timings(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (IS_ERR(timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return PTR_ERR(timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* clk_x period in picoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!t_x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * The bus interface clock, clk_x, is phase aligned with the core clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * The clk_x is an integral multiple N of the core clk. The value N is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * configured at IP delivery time, and its available value is 4, 5, 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (mult_x < 4 || mult_x > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) sel = &to_denali_chip(chip)->sels[chipnr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* tRWH -> RE_2_WE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) tmp = ioread32(denali->reg + RE_2_WE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) tmp &= ~RE_2_WE__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) sel->re_2_we = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* tRHZ -> RE_2_RE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) tmp = ioread32(denali->reg + RE_2_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tmp &= ~RE_2_RE__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) sel->re_2_re = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * tCCS, tWHR -> WE_2_RE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * With WE_2_RE properly set, the Denali controller automatically takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * care of the delay; the driver need not set NAND_WAIT_TCCS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) sel->hwhr2_and_we_2_re = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* tADL -> ADDR_2_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* for older versions, ADDR_2_DATA is only 6 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (denali->revision < 0x0501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) addr_2_data_mask >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) sel->tcwaw_and_addr_2_data = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* tREH, tWH -> RDWR_EN_HI_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) tmp &= ~RDWR_EN_HI_CNT__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) sel->rdwr_en_hi_cnt = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * tREA -> ACC_CLKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * tRP, tWP, tRHOH, tRC, tWC -> RDWR_EN_LO_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * Determine the minimum of acc_clks to meet the setup timing when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * capturing the incoming data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * The delay on the chip side is well-defined as tREA, but we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * take additional delay into account. This includes a certain degree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * of unknowledge, such as signal propagation delays on the PCB and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * in the SoC, load capacity of the I/O pins, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) acc_clks = DIV_ROUND_UP(timings->tREA_max + data_setup_on_host, t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* Determine the minimum of rdwr_en_lo_cnt from RE#/WE# pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Extend rdwr_en_lo to meet the data hold timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rdwr_en_lo = max_t(int, rdwr_en_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) acc_clks - timings->tRHOH_min / t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Extend rdwr_en_lo to meet the requirement for RE#/WE# cycle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) t_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Center the data latch timing for extra safety */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) acc_clks = (acc_clks + rdwr_en_lo +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DIV_ROUND_UP(timings->tRHOH_min, t_x)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tmp = ioread32(denali->reg + ACC_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) tmp &= ~ACC_CLKS__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sel->acc_clks = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tmp &= ~RDWR_EN_LO_CNT__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) sel->rdwr_en_lo_cnt = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* tCS, tCEA -> CS_SETUP_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) tmp = ioread32(denali->reg + CS_SETUP_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) tmp &= ~CS_SETUP_CNT__VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sel->cs_setup_cnt = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int denali_calc_ecc_bytes(int step_size, int strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) EXPORT_SYMBOL(denali_calc_ecc_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct nand_chip *chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (section > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) oobregion->offset = denali->oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) oobregion->length = chip->ecc.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int denali_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct nand_chip *chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (section > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) oobregion->length = mtd->oobsize - oobregion->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .ecc = denali_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .free = denali_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int denali_multidev_fixup(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct nand_memory_organization *memorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) memorg = nanddev_get_memorg(&chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Support for multi device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * When the IP configuration is x16 capable and two x8 chips are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * connected in parallel, DEVICES_CONNECTED should be set to 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * In this case, the core framework knows nothing about this fact,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * so we should tell it the _logical_ pagesize and anything necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * On some SoCs, DEVICES_CONNECTED is not auto-detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (denali->devs_per_cs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) denali->devs_per_cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) iowrite32(1, denali->reg + DEVICES_CONNECTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (denali->devs_per_cs == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (denali->devs_per_cs != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_err(denali->dev, "unsupported number of devices %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) denali->devs_per_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* 2 chips in parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) memorg->pagesize <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) memorg->oobsize <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mtd->size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mtd->erasesize <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) mtd->writesize <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mtd->oobsize <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) chip->page_shift += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) chip->phys_erase_shift += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) chip->bbt_erase_shift += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) chip->chip_shift += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) chip->pagemask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) chip->ecc.size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) chip->ecc.bytes <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) chip->ecc.strength <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) denali->oob_skip_bytes <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int denali_attach_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = nand_ecc_choose_conf(chip, denali->ecc_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mtd->oobsize - denali->oob_skip_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev_err(denali->dev, "Failed to setup ECC settings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_dbg(denali->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = denali_multidev_fixup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static void denali_exec_in8(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) u8 *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) buf[i] = denali->host_read(denali, type | DENALI_BANK(denali));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void denali_exec_in16(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u8 *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) for (i = 0; i < len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) data = denali->host_read(denali, type | DENALI_BANK(denali));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* bit 31:24 and 15:8 are used for DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) buf[i] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) buf[i + 1] = data >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void denali_exec_in(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u8 *buf, unsigned int len, bool width16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (width16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) denali_exec_in16(denali, type, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) denali_exec_in8(denali, type, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void denali_exec_out8(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const u8 *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) denali->host_write(denali, type | DENALI_BANK(denali), buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static void denali_exec_out16(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) const u8 *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) for (i = 0; i < len; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) denali->host_write(denali, type | DENALI_BANK(denali),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) buf[i + 1] << 16 | buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static void denali_exec_out(struct denali_controller *denali, u32 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) const u8 *buf, unsigned int len, bool width16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (width16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) denali_exec_out16(denali, type, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) denali_exec_out8(denali, type, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int denali_exec_waitrdy(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u32 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* R/B# pin transitioned from low to high? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) irq_stat = denali_wait_for_irq(denali, INTR__INT_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Just in case nand_operation has multiple NAND_OP_WAITRDY_INSTR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) denali_reset_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return irq_stat & INTR__INT_ACT ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int denali_exec_instr(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) const struct nand_op_instr *instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct denali_controller *denali = to_denali_controller(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) switch (instr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case NAND_OP_CMD_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) denali_exec_out8(denali, DENALI_MAP11_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) &instr->ctx.cmd.opcode, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case NAND_OP_ADDR_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) denali_exec_out8(denali, DENALI_MAP11_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) instr->ctx.addr.addrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) instr->ctx.addr.naddrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case NAND_OP_DATA_IN_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) denali_exec_in(denali, DENALI_MAP11_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) instr->ctx.data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) instr->ctx.data.len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) !instr->ctx.data.force_8bit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) chip->options & NAND_BUSWIDTH_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case NAND_OP_DATA_OUT_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) denali_exec_out(denali, DENALI_MAP11_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) instr->ctx.data.buf.out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) instr->ctx.data.len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) !instr->ctx.data.force_8bit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) chip->options & NAND_BUSWIDTH_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case NAND_OP_WAITRDY_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return denali_exec_waitrdy(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) WARN_ONCE(1, "unsupported NAND instruction type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) instr->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int denali_exec_op(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) const struct nand_operation *op, bool check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) denali_select_target(chip, op->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * Some commands contain NAND_OP_WAITRDY_INSTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * irq must be cleared here to catch the R/B# interrupt there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) denali_reset_irq(to_denali_controller(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) for (i = 0; i < op->ninstrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = denali_exec_instr(chip, &op->instrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const struct nand_controller_ops denali_controller_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .attach_chip = denali_attach_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .exec_op = denali_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .setup_interface = denali_setup_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int denali_chip_init(struct denali_controller *denali,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct denali_chip *dchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct nand_chip *chip = &dchip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct denali_chip *dchip2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int i, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) chip->controller = &denali->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* sanity checks for bank numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; i < dchip->nsels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned int bank = dchip->sels[i].bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (bank >= denali->nbanks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_err(denali->dev, "unsupported bank %d\n", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) for (j = 0; j < i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (bank == dchip->sels[j].bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(denali->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "bank %d is assigned twice in the same chip\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) list_for_each_entry(dchip2, &denali->chips, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) for (j = 0; j < dchip2->nsels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (bank == dchip2->sels[j].bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_err(denali->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "bank %d is already used\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) mtd->dev.parent = denali->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * Fallback to the default name if DT did not give "label" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Use "label" property if multiple chips are connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (!mtd->name && list_empty(&denali->chips))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) mtd->name = "denali-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (denali->dma_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) chip->options |= NAND_USES_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) chip->buf_align = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* clk rate info is needed for setup_interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!denali->clk_rate || !denali->clk_x_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) chip->options |= NAND_KEEP_TIMINGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) chip->bbt_options |= NAND_BBT_USE_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) chip->bbt_options |= NAND_BBT_NO_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) chip->options |= NAND_NO_SUBPAGE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) chip->ecc.read_page = denali_read_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) chip->ecc.write_page = denali_write_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) chip->ecc.read_page_raw = denali_read_page_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) chip->ecc.write_page_raw = denali_write_page_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) chip->ecc.read_oob = denali_read_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) chip->ecc.write_oob = denali_write_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = nand_scan(chip, dchip->nsels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = mtd_device_register(mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto cleanup_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) list_add_tail(&dchip->node, &denali->chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) cleanup_nand:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) EXPORT_SYMBOL_GPL(denali_chip_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int denali_init(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u32 features = ioread32(denali->reg + FEATURES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) nand_controller_init(&denali->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) denali->controller.ops = &denali_controller_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) init_completion(&denali->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) spin_lock_init(&denali->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) INIT_LIST_HEAD(&denali->chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) denali->active_bank = DENALI_INVALID_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * The REVISION register may not be reliable. Platforms are allowed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * override it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (!denali->revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) denali->revision = swab16(ioread32(denali->reg + REVISION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) denali->nbanks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* the encoding changed from rev 5.0 to 5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (denali->revision < 0x0501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) denali->nbanks <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (features & FEATURES__DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) denali->dma_avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (denali->dma_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_info(denali->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "Failed to set DMA mask. Disabling DMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) denali->dma_avail = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (denali->dma_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (denali->caps & DENALI_CAP_DMA_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) denali->setup_dma = denali_setup_dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) denali->setup_dma = denali_setup_dma32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (features & FEATURES__INDEX_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) denali->host_read = denali_indexed_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) denali->host_write = denali_indexed_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) denali->host_read = denali_direct_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) denali->host_write = denali_direct_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Set how many bytes should be skipped before writing data in OOB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * If a platform requests a non-zero value, set it to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * Otherwise, read the value out, expecting it has already been set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * by firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (denali->oob_skip_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) iowrite32(denali->oob_skip_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) denali->reg + SPARE_AREA_SKIP_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) denali->oob_skip_bytes = ioread32(denali->reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) SPARE_AREA_SKIP_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) iowrite32(0, denali->reg + TRANSFER_SPARE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) denali_clear_irq_all(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) IRQF_SHARED, DENALI_NAND_NAME, denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(denali->dev, "Unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) denali_enable_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) EXPORT_SYMBOL(denali_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) void denali_remove(struct denali_controller *denali)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct denali_chip *dchip, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct nand_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) list_for_each_entry_safe(dchip, tmp, &denali->chips, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) chip = &dchip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = mtd_device_unregister(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) list_del(&dchip->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) denali_disable_irq(denali);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) EXPORT_SYMBOL(denali_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MODULE_DESCRIPTION("Driver core for Denali NAND controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) MODULE_AUTHOR("Intel Corporation and its suppliers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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