^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence NAND flash controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Cadence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Piotr Sroka <piotrs@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * HPNFC can work in 3 modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - PIO - can work in master or slave DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - CDMA - needs Master DMA for accessing command descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - Generic mode - can use only slave DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CDMA and PIO modes can be used to execute only base commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Generic mode can be used to execute any command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * on NAND flash memory. Driver uses CDMA mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * block erasing, page reading, page programing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Generic mode is used for executing rest of commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_ADDRESS_CYC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX_ERASE_ADDRESS_CYC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_DATA_SIZE 0xFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_DATA_SIZE_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Register definition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Command register 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Writing data to this register will initiate a new transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * of the NF controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMD_REG0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Command type field mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMD_REG0_CT GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Command type CDMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMD_REG0_CT_CDMA 0uL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Command type generic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMD_REG0_CT_GEN 3uL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Command thread number field mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMD_REG0_TN GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Command register 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMD_REG2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Command register 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMD_REG3 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Pointer register to select which thread status will be selected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMD_STATUS_PTR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Command status register for selected thread. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMD_STATUS 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Interrupt status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define INTR_STATUS 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INTR_STATUS_SDMA_ERR BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define INTR_STATUS_SDMA_TRIGG BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define INTR_STATUS_UNSUPP_CMD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define INTR_STATUS_DDMA_TERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INTR_STATUS_CDMA_TERR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define INTR_STATUS_CDMA_IDL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Interrupt enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define INTR_ENABLE 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define INTR_ENABLE_INTR_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INTR_ENABLE_SDMA_ERR_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INTR_ENABLE_SDMA_TRIGG_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define INTR_ENABLE_UNSUPP_CMD_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define INTR_ENABLE_DDMA_TERR_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INTR_ENABLE_CDMA_TERR_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define INTR_ENABLE_CDMA_IDLE_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Controller internal state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CTRL_STATUS 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CTRL_STATUS_INIT_COMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CTRL_STATUS_CTRL_BUSY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Command Engine threads state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TRD_STATUS 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Command Engine interrupt thread error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TRD_ERR_INT_STATUS 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Command Engine interrupt thread error enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TRD_ERR_INT_STATUS_EN 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Command Engine interrupt thread complete status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TRD_COMP_INT_STATUS 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Transfer config 0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Configures data transfer parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TRAN_CFG_0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Offset value from the beginning of the page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TRAN_CFG_0_OFFSET GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Numbers of sectors to transfer within singlNF device's page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TRAN_CFG_0_SEC_CNT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Transfer config 1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Configures data transfer parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TRAN_CFG_1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Size of last data sector. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Size of not-last data sector. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* ECC engine configuration register 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ECC_CONFIG_0 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Correction strength. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ECC_CONFIG_0_CORR_STR GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Enable erased pages detection mechanism. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ECC_CONFIG_0_ERASE_DET_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Enable controller ECC check bits generation and correction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ECC_CONFIG_0_ECC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* ECC engine configuration register 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ECC_CONFIG_1 0x042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Multiplane settings register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MULTIPLANE_CFG 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Cache operation settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CACHE_CFG 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* DMA settings register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DMA_SETINGS 0x043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Enable SDMA error report on access unprepared slave DMA interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DMA_SETINGS_SDMA_ERR_RSP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Transferred data block size for the slave DMA module. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SDMA_SIZE 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Thread number associated with transferred data block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * for the slave DMA module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SDMA_TRD_NUM 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Thread number mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CONTROL_DATA_CTRL 0x0494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Thread number mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CTRL_VERSION 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CTRL_VERSION_REV GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Available hardware features of the controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CTRL_FEATURES 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Support for NV-DDR2/3 work mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CTRL_FEATURES_NVDDR_2_3 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Support for NV-DDR work mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CTRL_FEATURES_NVDDR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Support for asynchronous work mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CTRL_FEATURES_ASYNC BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Support for asynchronous work mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CTRL_FEATURES_N_BANKS GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Slave and Master DMA data width. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CTRL_FEATURES_DMA_DWITH64 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Availability of Control Data feature.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CTRL_FEATURES_CONTROL_DATA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* BCH Engine identification register 0 - correction strengths. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BCH_CFG_0 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* BCH Engine identification register 1 - correction strengths. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BCH_CFG_1 0x83C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* BCH Engine identification register 2 - sector sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BCH_CFG_2 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BCH_CFG_2_SECT_0 GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BCH_CFG_2_SECT_1 GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* BCH Engine identification register 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BCH_CFG_3 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Ready/Busy# line status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RBN_SETINGS 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Common settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define COMMON_SET 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* 16 bit device connected to the NAND Flash interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define COMMON_SET_DEVICE_16BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Skip_bytes registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SKIP_BYTES_CONF 0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SKIP_BYTES_OFFSET 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Timings configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ASYNC_TOGGLE_TIMINGS 0x101c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TIMINGS0 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TIMINGS0_TADL GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TIMINGS0_TCCS GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TIMINGS0_TWHR GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TIMINGS0_TRHW GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TIMINGS1 0x1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TIMINGS1_TRHZ GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TIMINGS1_TWB GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TIMINGS1_TVDLY GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TIMINGS2 0x102c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TIMINGS2_TFEAT GENMASK(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Configuration of the resynchronization of slave DLL of PHY. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DLL_PHY_CTRL 0x1034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DLL_PHY_CTRL_DLL_RST_N BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Register controlling DQ related timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PHY_DQ_TIMING 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Register controlling DSQ related timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PHY_DQS_TIMING 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Register controlling the gate and loopback control related timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PHY_GATE_LPBK_CTRL 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Register holds the control for the master DLL logic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PHY_DLL_MASTER_CTRL 0x200C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Register holds the control for the slave DLL logic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PHY_DLL_SLAVE_CTRL 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* This register handles the global control settings for the PHY. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PHY_CTRL 0x2080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PHY_CTRL_SDR_DQS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PHY_CTRL_PHONY_DQS GENMASK(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * This register handles the global control settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * for the termination selects for reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PHY_TSEL 0x2084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Generic command layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GCMD_LAY_CS GENMASK_ULL(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * This bit informs the minicotroller if it has to wait for tWB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * after sending the last CMD/ADDR/DATA in the sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GCMD_LAY_TWB BIT_ULL(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Type of generic instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GCMD_LAY_INSTR GENMASK_ULL(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Generic CMD sequence type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GCMD_LAY_INSTR_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Generic ADDR sequence type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GCMD_LAY_INSTR_ADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Generic data transfer sequence type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GCMD_LAY_INSTR_DATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Input part of generic command type of input is command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Generic command address sequence - address fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Generic command address sequence - address size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Transfer direction field of generic command data sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GCMD_DIR BIT_ULL(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Read transfer direction of generic command data sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GCMD_DIR_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Write transfer direction of generic command data sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GCMD_DIR_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* ECC enabled flag of generic command data sequence - ECC enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GCMD_ECC_EN BIT_ULL(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Generic command data sequence - sector size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GCMD_SECT_SIZE GENMASK_ULL(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Generic command data sequence - sector count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GCMD_SECT_CNT GENMASK_ULL(39, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Generic command data sequence - last sector size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GCMD_LAST_SIZE GENMASK_ULL(55, 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* CDMA descriptor fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Erase command type of CDMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CDMA_CT_ERASE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Program page command type of CDMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CDMA_CT_WR 0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Read page command type of CDMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CDMA_CT_RD 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Flash pointer memory shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CDMA_CFPTR_MEM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Flash pointer memory mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CDMA_CFPTR_MEM GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Command DMA descriptor flags. If set causes issue interrupt after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * the completion of descriptor processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CDMA_CF_INT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Command DMA descriptor flags - the next descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * address field is valid and descriptor processing should continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CDMA_CF_CONT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* DMA master flag of command DMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CDMA_CF_DMA_MASTER BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Operation complete status of command descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CDMA_CS_COMP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Operation complete status of command descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Command descriptor status - operation fail. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CDMA_CS_FAIL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Command descriptor status - page erased. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CDMA_CS_ERP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Command descriptor status - timeout occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CDMA_CS_TOUT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Maximum amount of correction applied to one ECC sector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * It is part of command descriptor status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CDMA_CS_MAXERR GENMASK(9, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Command descriptor status - uncorrectable ECC error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CDMA_CS_UNCE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Command descriptor status - descriptor error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CDMA_CS_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Status of operation - OK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define STAT_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Status of operation - FAIL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define STAT_FAIL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Status of operation - uncorrectable ECC error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define STAT_ECC_UNCORR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Status of operation - page erased. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define STAT_ERASED 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Status of operation - correctable ECC error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define STAT_ECC_CORR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Status of operation - unsuspected state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define STAT_UNKNOWN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Status of operation - operation is not completed yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define STAT_BUSY 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BCH_MAX_NUM_CORR_CAPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define BCH_MAX_NUM_SECTOR_SIZES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct cadence_nand_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 async_toggle_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 timings0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 timings1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 timings2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 dll_phy_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 phy_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 phy_dqs_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 phy_gate_lpbk_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Command DMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct cadence_nand_cdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Next descriptor address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u64 next_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 flash_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*field appears in HPNFC version 13*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Operation the controller needs to perform. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 command_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Flags for operation of this command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 command_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u16 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* System/host memory address required for data DMA commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u64 memory_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Status of operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Address pointer to sync buffer location. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u64 sync_flag_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Controls the buffer sync mechanism. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 sync_arguments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Control data pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u64 ctrl_data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Interrupt status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct cadence_nand_irq_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Thread operation complete status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 trd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Thread operation error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 trd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Controller status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Cadence NAND flash controller capabilities get from driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct cadence_nand_dt_devdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Skew value of the output signals of the NAND Flash interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 if_skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* It informs if slave DMA interface is connected to DMA engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int has_dma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Cadence NAND flash controller capabilities read from registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct cdns_nand_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Maximum number of banks supported by hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 max_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Slave and Master DMA data width in bytes (4 or 8). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 data_dma_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Control Data feature supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bool data_control_supp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Is PHY type DLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bool is_phy_type_dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct cdns_nand_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct nand_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct cadence_nand_cdma_desc *cdma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* IP capability. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct cadence_nand_dt_devdata *caps1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct cdns_nand_caps caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 ctrl_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dma_addr_t dma_cdma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 curr_corr_str_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Register interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void __iomem *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Interrupts that have happened. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct cadence_nand_irq_status irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Interrupts we are waiting for. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct cadence_nand_irq_status irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Protect irq_mask and irq_status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ecc_strengths[BCH_MAX_NUM_CORR_CAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct nand_ecc_caps ecc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int curr_trans_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct dma_chan *dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 nf_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Estimated Board delay. The value includes the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * round trip delay for the signals and is used for deciding on values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * associated with data read capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 board_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct nand_chip *selected_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned long assigned_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct list_head chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 bch_metadata_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct cdns_nand_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cadence_nand_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct nand_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 nsels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * part of oob area of NAND flash memory page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * This part is available for user to read or write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Sector size. There are few sectors per mtd->writesize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Offset of BBM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u8 bbm_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Number of bytes reserved for BBM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 bbm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* ECC strength index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 corr_str_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 cs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct ecc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int (*calc_ecc_bytes)(int step_size, int strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int max_step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static inline struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cdns_nand_chip *to_cdns_nand_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return container_of(chip, struct cdns_nand_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static inline struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cdns_nand_ctrl *to_cdns_nand_ctrl(struct nand_controller *controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return container_of(controller, struct cdns_nand_ctrl, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cadence_nand_dma_buf_ok(struct cdns_nand_ctrl *cdns_ctrl, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 data_dma_width = cdns_ctrl->caps2.data_dma_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return buf && virt_addr_valid(buf) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) likely(IS_ALIGNED((uintptr_t)buf, data_dma_width)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) likely(IS_ALIGNED(buf_len, DMA_DATA_SIZE_ALIGN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int cadence_nand_wait_for_value(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 reg_offset, u32 timeout_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 mask, bool is_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) val, !(val & mask) == is_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 10, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "Timeout while waiting for reg %x with mask %x is clear %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) reg_offset, mask, is_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int cadence_nand_set_ecc_enable(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) reg |= ECC_CONFIG_0_ECC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) reg &= ~ECC_CONFIG_0_ECC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void cadence_nand_set_ecc_strength(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 corr_str_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (cdns_ctrl->curr_corr_str_idx == corr_str_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) reg &= ~ECC_CONFIG_0_CORR_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) reg |= FIELD_PREP(ECC_CONFIG_0_CORR_STR, corr_str_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cdns_ctrl->curr_corr_str_idx = corr_str_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int cadence_nand_get_ecc_strength_idx(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int i, corr_str_idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (cdns_ctrl->ecc_strengths[i] == strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) corr_str_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return corr_str_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int cadence_nand_set_skip_marker_val(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u16 marker_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) reg &= ~SKIP_BYTES_MARKER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) reg |= FIELD_PREP(SKIP_BYTES_MARKER_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) marker_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int cadence_nand_set_skip_bytes_conf(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8 num_of_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 offset_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 reg, skip_bytes_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) num_of_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) offset_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) reg &= ~SKIP_BYTES_NUM_OF_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) reg |= FIELD_PREP(SKIP_BYTES_NUM_OF_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) num_of_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) skip_bytes_offset = FIELD_PREP(SKIP_BYTES_OFFSET_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) offset_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Functions enables/disables hardware detection of erased data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static void cadence_nand_set_erase_detection(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bool enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 bitflips_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reg |= ECC_CONFIG_0_ERASE_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reg &= ~ECC_CONFIG_0_ERASE_DET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int cadence_nand_set_access_width16(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bool bit_bus16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) reg = readl_relaxed(cdns_ctrl->reg + COMMON_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!bit_bus16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) reg &= ~COMMON_SET_DEVICE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) reg |= COMMON_SET_DEVICE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cadence_nand_clear_interrupt(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct cadence_nand_irq_status *irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel_relaxed(irq_status->trd_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cdns_ctrl->reg + TRD_COMP_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writel_relaxed(irq_status->trd_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cdns_ctrl->reg + TRD_ERR_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cadence_nand_read_int_status(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct cadence_nand_irq_status *irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) irq_status->trd_status = readl_relaxed(cdns_ctrl->reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) + TRD_COMP_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) irq_status->trd_error = readl_relaxed(cdns_ctrl->reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) + TRD_ERR_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static u32 irq_detected(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct cadence_nand_irq_status *irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) cadence_nand_read_int_status(cdns_ctrl, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return irq_status->status || irq_status->trd_status ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) irq_status->trd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static void cadence_nand_reset_irq(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_lock_irqsave(&cdns_ctrl->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) memset(&cdns_ctrl->irq_status, 0, sizeof(cdns_ctrl->irq_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) memset(&cdns_ctrl->irq_mask, 0, sizeof(cdns_ctrl->irq_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) spin_unlock_irqrestore(&cdns_ctrl->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * This is the interrupt service routine. It handles all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * sent to this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static irqreturn_t cadence_nand_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct cdns_nand_ctrl *cdns_ctrl = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct cadence_nand_irq_status irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) irqreturn_t result = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_lock(&cdns_ctrl->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (irq_detected(cdns_ctrl, &irq_status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Handle interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* First acknowledge it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cadence_nand_clear_interrupt(cdns_ctrl, &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Status in the device context for someone to read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cdns_ctrl->irq_status.status |= irq_status.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cdns_ctrl->irq_status.trd_status |= irq_status.trd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cdns_ctrl->irq_status.trd_error |= irq_status.trd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Notify anyone who cares that it happened. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) complete(&cdns_ctrl->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Tell the OS that we've handled this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) result = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) spin_unlock(&cdns_ctrl->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void cadence_nand_set_irq_mask(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct cadence_nand_irq_status *irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) cdns_ctrl->reg + INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) writel_relaxed(irq_mask->trd_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) cdns_ctrl->reg + TRD_ERR_INT_STATUS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) cadence_nand_wait_for_irq(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct cadence_nand_irq_status *irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct cadence_nand_irq_status *irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned long timeout = msecs_to_jiffies(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) time_left = wait_for_completion_timeout(&cdns_ctrl->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) *irq_status = cdns_ctrl->irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Timeout error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(cdns_ctrl->dev, "timeout occurred:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(cdns_ctrl->dev, "\tstatus = 0x%x, mask = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) irq_status->status, irq_mask->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "\ttrd_status = 0x%x, trd_status mask = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) irq_status->trd_status, irq_mask->trd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "\t trd_error = 0x%x, trd_error mask = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) irq_status->trd_error, irq_mask->trd_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Execute generic command on NAND controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int cadence_nand_generic_cmd_send(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u8 chip_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u64 mini_ctrl_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 mini_ctrl_cmd_l, mini_ctrl_cmd_h, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_CS, chip_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mini_ctrl_cmd_l = mini_ctrl_cmd & 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mini_ctrl_cmd_h = mini_ctrl_cmd >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) cadence_nand_reset_irq(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) writel_relaxed(mini_ctrl_cmd_l, cdns_ctrl->reg + CMD_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writel_relaxed(mini_ctrl_cmd_h, cdns_ctrl->reg + CMD_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Select generic command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Thread number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) reg |= FIELD_PREP(CMD_REG0_TN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Issue command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Wait for data on slave DMA interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int cadence_nand_wait_on_sdma(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u8 *out_sdma_trd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 *out_sdma_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct cadence_nand_irq_status irq_mask, irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) irq_mask.trd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) irq_mask.trd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) irq_mask.status = INTR_STATUS_SDMA_TRIGG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) | INTR_STATUS_SDMA_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) | INTR_STATUS_UNSUPP_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) cadence_nand_set_irq_mask(cdns_ctrl, &irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cadence_nand_wait_for_irq(cdns_ctrl, &irq_mask, &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (irq_status.status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_err(cdns_ctrl->dev, "Timeout while waiting for SDMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (irq_status.status & INTR_STATUS_SDMA_TRIGG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *out_sdma_size = readl_relaxed(cdns_ctrl->reg + SDMA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) *out_sdma_trd = readl_relaxed(cdns_ctrl->reg + SDMA_TRD_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *out_sdma_trd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) FIELD_GET(SDMA_TRD_NUM_SDMA_TRD, *out_sdma_trd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(cdns_ctrl->dev, "SDMA error - irq_status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) irq_status.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static void cadence_nand_get_caps(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) reg = readl_relaxed(cdns_ctrl->reg + CTRL_FEATURES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (FIELD_GET(CTRL_FEATURES_DMA_DWITH64, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cdns_ctrl->caps2.data_dma_width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cdns_ctrl->caps2.data_dma_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (reg & CTRL_FEATURES_CONTROL_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) cdns_ctrl->caps2.data_control_supp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (reg & (CTRL_FEATURES_NVDDR_2_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) | CTRL_FEATURES_NVDDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cdns_ctrl->caps2.is_phy_type_dll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Prepare CDMA descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dma_addr_t ctrl_data_ptr, u16 ctype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) memset(cdma_desc, 0, sizeof(struct cadence_nand_cdma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Set fields for one descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) cdma_desc->flash_pointer = flash_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (cdns_ctrl->ctrl_rev >= 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cdma_desc->bank = nf_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) cdma_desc->command_flags |= CDMA_CF_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) cdma_desc->memory_pointer = mem_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) cdma_desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) cdma_desc->sync_flag_pointer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) cdma_desc->sync_arguments = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) cdma_desc->command_type = ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 desc_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (desc_status & CDMA_CS_ERP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return STAT_ERASED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (desc_status & CDMA_CS_UNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return STAT_ECC_UNCORR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (desc_status & CDMA_CS_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_err(cdns_ctrl->dev, ":CDMA desc error flag detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return STAT_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (FIELD_GET(CDMA_CS_MAXERR, desc_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return STAT_ECC_CORR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return STAT_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int cadence_nand_cdma_finish(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct cadence_nand_cdma_desc *desc_ptr = cdns_ctrl->cdma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 status = STAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (desc_ptr->status & CDMA_CS_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) status = cadence_nand_check_desc_error(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) desc_ptr->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(cdns_ctrl->dev, ":CDMA error %x\n", desc_ptr->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } else if (desc_ptr->status & CDMA_CS_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Descriptor finished with no errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (desc_ptr->command_flags & CDMA_CF_CONT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_info(cdns_ctrl->dev, "DMA unsupported flag is set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) status = STAT_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* Last descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) status = STAT_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int cadence_nand_cdma_send(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Wait for thread ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) status = cadence_nand_wait_for_value(cdns_ctrl, TRD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) BIT(thread), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) cadence_nand_reset_irq(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) reinit_completion(&cdns_ctrl->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) writel_relaxed((u32)cdns_ctrl->dma_cdma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) cdns_ctrl->reg + CMD_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) writel_relaxed(0, cdns_ctrl->reg + CMD_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Select CDMA mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_CDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Thread number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) reg |= FIELD_PREP(CMD_REG0_TN, thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Issue command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Send SDMA command and wait for finish. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) cadence_nand_cdma_send_and_wait(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u8 thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct cadence_nand_irq_status irq_mask, irq_status = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) irq_mask.trd_status = BIT(thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) irq_mask.trd_error = BIT(thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) irq_mask.status = INTR_STATUS_CDMA_TERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) cadence_nand_set_irq_mask(cdns_ctrl, &irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) status = cadence_nand_cdma_send(cdns_ctrl, thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) cadence_nand_wait_for_irq(cdns_ctrl, &irq_mask, &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (irq_status.status == 0 && irq_status.trd_status == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) irq_status.trd_error == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev_err(cdns_ctrl->dev, "CDMA command timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (irq_status.status & irq_mask.status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_err(cdns_ctrl->dev, "CDMA command failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * ECC size depends on configured ECC strength and on maximum supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * ECC step size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int cadence_nand_calc_ecc_bytes(int max_step_size, int strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int nbytes = DIV_ROUND_UP(fls(8 * max_step_size) * strength, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return ALIGN(nbytes, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define CADENCE_NAND_CALC_ECC_BYTES(max_step_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) cadence_nand_calc_ecc_bytes_##max_step_size(int step_size, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int strength)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return cadence_nand_calc_ecc_bytes(max_step_size, strength);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) CADENCE_NAND_CALC_ECC_BYTES(256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) CADENCE_NAND_CALC_ECC_BYTES(512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) CADENCE_NAND_CALC_ECC_BYTES(1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) CADENCE_NAND_CALC_ECC_BYTES(2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) CADENCE_NAND_CALC_ECC_BYTES(4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Function reads BCH capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int cadence_nand_read_bch_caps(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct nand_ecc_caps *ecc_caps = &cdns_ctrl->ecc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int max_step_size = 0, nstrengths, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (cdns_ctrl->bch_metadata_size < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "Driver needs at least 4 bytes of BCH meta data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) cdns_ctrl->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) cdns_ctrl->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) cdns_ctrl->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) cdns_ctrl->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) cdns_ctrl->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) cdns_ctrl->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) cdns_ctrl->ecc_stepinfos[0].stepsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FIELD_GET(BCH_CFG_2_SECT_0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) cdns_ctrl->ecc_stepinfos[1].stepsize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) FIELD_GET(BCH_CFG_2_SECT_1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) nstrengths = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (cdns_ctrl->ecc_strengths[i] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) nstrengths++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ecc_caps->nstepinfos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) for (i = 0; i < BCH_MAX_NUM_SECTOR_SIZES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* ECC strengths are common for all step infos. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) cdns_ctrl->ecc_stepinfos[i].nstrengths = nstrengths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) cdns_ctrl->ecc_stepinfos[i].strengths =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) cdns_ctrl->ecc_strengths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (cdns_ctrl->ecc_stepinfos[i].stepsize != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ecc_caps->nstepinfos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (cdns_ctrl->ecc_stepinfos[i].stepsize > max_step_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) max_step_size = cdns_ctrl->ecc_stepinfos[i].stepsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ecc_caps->stepinfos = &cdns_ctrl->ecc_stepinfos[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) switch (max_step_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case 1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) case 2048:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case 4096:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "Unsupported sector size(ecc step size) %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) max_step_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Hardware initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) status = cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) CTRL_STATUS_INIT_COMP, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) reg = readl_relaxed(cdns_ctrl->reg + CTRL_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) cdns_ctrl->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_info(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "%s: cadence nand controller version reg %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Disable cache and multiplane. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* Clear all interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) cadence_nand_get_caps(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (cadence_nand_read_bch_caps(cdns_ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Set IO width access to 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * It is because during SW device discovering width access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * is expected to be 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) status = cadence_nand_set_access_width16(cdns_ctrl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define TT_MAIN_OOB_AREAS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define TT_RAW_PAGE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define TT_BBM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define TT_MAIN_OOB_AREA_EXT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Prepare size of data to transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) cadence_nand_prepare_data_size(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int transfer_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u32 sec_size = 0, offset = 0, sec_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 last_sec_size = cdns_chip->sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u32 data_ctrl_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (cdns_ctrl->curr_trans_type == transfer_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) switch (transfer_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) case TT_MAIN_OOB_AREA_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) sec_cnt = cdns_chip->sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sec_size = cdns_chip->sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) data_ctrl_size = cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) case TT_MAIN_OOB_AREAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) sec_cnt = cdns_chip->sector_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) last_sec_size = cdns_chip->sector_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) + cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) sec_size = cdns_chip->sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case TT_RAW_PAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) last_sec_size = mtd->writesize + mtd->oobsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case TT_BBM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) offset = mtd->writesize + cdns_chip->bbm_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) last_sec_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) reg |= FIELD_PREP(TRAN_CFG_0_OFFSET, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) reg |= FIELD_PREP(TRAN_CFG_1_LAST_SEC_SIZE, last_sec_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) reg |= FIELD_PREP(TRAN_CFG_1_SECTOR_SIZE, sec_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (cdns_ctrl->caps2.data_control_supp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) reg = readl_relaxed(cdns_ctrl->reg + CONTROL_DATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) reg &= ~CONTROL_DATA_CTRL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) reg |= FIELD_PREP(CONTROL_DATA_CTRL_SIZE, data_ctrl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) writel_relaxed(reg, cdns_ctrl->reg + CONTROL_DATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) cdns_ctrl->curr_trans_type = transfer_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) cadence_nand_cdma_transfer(struct cdns_nand_ctrl *cdns_ctrl, u8 chip_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int page, void *buf, void *ctrl_dat, u32 buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) u32 ctrl_dat_size, enum dma_data_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) bool with_ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dma_addr_t dma_buf, dma_ctrl_dat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u8 thread_nr = chip_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u16 ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (dir == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ctype = CDMA_CT_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ctype = CDMA_CT_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) cadence_nand_set_ecc_enable(cdns_ctrl, with_ecc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dma_buf = dma_map_single(cdns_ctrl->dev, buf, buf_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (dma_mapping_error(cdns_ctrl->dev, dma_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (ctrl_dat && ctrl_dat_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dma_ctrl_dat = dma_map_single(cdns_ctrl->dev, ctrl_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ctrl_dat_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (dma_mapping_error(cdns_ctrl->dev, dma_ctrl_dat)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dma_unmap_single(cdns_ctrl->dev, dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) buf_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dma_buf, dma_ctrl_dat, ctype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dma_unmap_single(cdns_ctrl->dev, dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) buf_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (ctrl_dat && ctrl_dat_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dma_unmap_single(cdns_ctrl->dev, dma_ctrl_dat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ctrl_dat_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return cadence_nand_cdma_finish(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static void cadence_nand_set_timings(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct cadence_nand_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) writel_relaxed(t->async_toggle_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (cdns_ctrl->caps2.is_phy_type_dll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (cdns_ctrl->caps2.is_phy_type_dll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) writel_relaxed(0, cdns_ctrl->reg + PHY_TSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) writel_relaxed(2, cdns_ctrl->reg + PHY_DQ_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) writel_relaxed(t->phy_dqs_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) cdns_ctrl->reg + PHY_DQS_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) writel_relaxed(t->phy_gate_lpbk_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) cdns_ctrl->reg + PHY_GATE_LPBK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) cdns_ctrl->reg + PHY_DLL_MASTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) writel_relaxed(0, cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static int cadence_nand_select_target(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (chip == cdns_ctrl->selected_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) cadence_nand_set_timings(cdns_ctrl, &cdns_chip->timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) cadence_nand_set_ecc_strength(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) cdns_chip->corr_str_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) cadence_nand_set_erase_detection(cdns_ctrl, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) chip->ecc.strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) cdns_ctrl->curr_trans_type = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) cdns_ctrl->selected_chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int cadence_nand_erase(struct nand_chip *chip, u32 page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u8 thread_nr = cdns_chip->cs[chip->cur_cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) cadence_nand_cdma_desc_prepare(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) CDMA_CT_ERASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(cdns_ctrl->dev, "erase operation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) status = cadence_nand_cdma_finish(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int cadence_nand_read_bbm(struct nand_chip *chip, int page, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) cadence_nand_prepare_data_size(chip, TT_BBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * Read only bad block marker from offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * defined by a memory manufacturer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) status = cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) page, cdns_ctrl->buf, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mtd->oobsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) 0, DMA_FROM_DEVICE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_err(cdns_ctrl->dev, "read BBM failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) memcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static int cadence_nand_write_page(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) const u8 *buf, int oob_required,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u16 marker_val = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) status = cadence_nand_select_target(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) mtd->writesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) + cdns_chip->bbm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (oob_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) marker_val = *(u16 *)(chip->oob_poi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) + cdns_chip->bbm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* Set oob data to 0xFF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) memset(cdns_ctrl->buf + mtd->writesize, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) cdns_chip->avail_oob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) cadence_nand_set_skip_marker_val(cdns_ctrl, marker_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREA_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) cdns_ctrl->caps2.data_control_supp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) u8 *oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (oob_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) oob = chip->oob_poi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) oob = cdns_ctrl->buf + mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) status = cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) page, (void *)buf, oob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) mtd->writesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) cdns_chip->avail_oob_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) DMA_TO_DEVICE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_err(cdns_ctrl->dev, "write page failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (oob_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Transfer the data to the oob area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) memcpy(cdns_ctrl->buf + mtd->writesize, chip->oob_poi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) cdns_chip->avail_oob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) memcpy(cdns_ctrl->buf, buf, mtd->writesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) page, cdns_ctrl->buf, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) mtd->writesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) + cdns_chip->avail_oob_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) 0, DMA_TO_DEVICE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static int cadence_nand_write_oob(struct nand_chip *chip, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) memset(cdns_ctrl->buf, 0xFF, mtd->writesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return cadence_nand_write_page(chip, cdns_ctrl->buf, 1, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int cadence_nand_write_page_raw(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) const u8 *buf, int oob_required,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int writesize = mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int oobsize = mtd->oobsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int ecc_steps = chip->ecc.steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) int ecc_size = chip->ecc.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int ecc_bytes = chip->ecc.bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) void *tmp_buf = cdns_ctrl->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) int oob_skip = cdns_chip->bbm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) size_t size = writesize + oobsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) int i, pos, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) status = cadence_nand_select_target(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * Fill the buffer with 0xff first except the full page transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * This simplifies the logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!buf || !oob_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) memset(tmp_buf, 0xff, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* Arrange the buffer for syndrome payload/ecc layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) for (i = 0; i < ecc_steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pos = i * (ecc_size + ecc_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) len = ecc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (pos >= writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) else if (pos + len > writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) len = writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) memcpy(tmp_buf + pos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (len < ecc_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) len = ecc_size - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) memcpy(tmp_buf + writesize + oob_skip, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (oob_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) const u8 *oob = chip->oob_poi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) u32 oob_data_offset = (cdns_chip->sector_count - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) (cdns_chip->sector_size + chip->ecc.bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) + cdns_chip->sector_size + oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* BBM at the beginning of the OOB area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) memcpy(tmp_buf + writesize, oob, oob_skip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* OOB free. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) memcpy(tmp_buf + oob_data_offset, oob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) cdns_chip->avail_oob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) oob += cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* OOB ECC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) for (i = 0; i < ecc_steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) pos = ecc_size + i * (ecc_size + ecc_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (i == (ecc_steps - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pos += cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) len = ecc_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (pos >= writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) else if (pos + len > writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) len = writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) memcpy(tmp_buf + pos, oob, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) oob += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (len < ecc_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) len = ecc_bytes - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) memcpy(tmp_buf + writesize + oob_skip, oob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) oob += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) cadence_nand_prepare_data_size(chip, TT_RAW_PAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) page, cdns_ctrl->buf, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mtd->writesize +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) mtd->oobsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) 0, DMA_TO_DEVICE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static int cadence_nand_write_oob_raw(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return cadence_nand_write_page_raw(chip, NULL, true, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static int cadence_nand_read_page(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u8 *buf, int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) int ecc_err_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) status = cadence_nand_select_target(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) mtd->writesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) + cdns_chip->bbm_offs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * If data buffer can be accessed by DMA and data_control feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * is supported then transfer data and oob directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) cdns_ctrl->caps2.data_control_supp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) u8 *oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (oob_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) oob = chip->oob_poi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) oob = cdns_ctrl->buf + mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREA_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) status = cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) page, buf, oob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) mtd->writesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) cdns_chip->avail_oob_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) DMA_FROM_DEVICE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* Otherwise use bounce buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) status = cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) page, cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) NULL, mtd->writesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) + cdns_chip->avail_oob_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) 0, DMA_FROM_DEVICE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) memcpy(buf, cdns_ctrl->buf, mtd->writesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (oob_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) memcpy(chip->oob_poi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) cdns_ctrl->buf + mtd->writesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) mtd->oobsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) case STAT_ECC_UNCORR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) mtd->ecc_stats.failed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ecc_err_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) case STAT_ECC_CORR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ecc_err_count = FIELD_GET(CDMA_CS_MAXERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) cdns_ctrl->cdma_desc->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) mtd->ecc_stats.corrected += ecc_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case STAT_ERASED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case STAT_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) dev_err(cdns_ctrl->dev, "read page failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (oob_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (cadence_nand_read_bbm(chip, page, chip->oob_poi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return ecc_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* Reads OOB data from the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static int cadence_nand_read_oob(struct nand_chip *chip, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return cadence_nand_read_page(chip, cdns_ctrl->buf, 1, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int cadence_nand_read_page_raw(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u8 *buf, int oob_required, int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) int oob_skip = cdns_chip->bbm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) int writesize = mtd->writesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int ecc_steps = chip->ecc.steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) int ecc_size = chip->ecc.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int ecc_bytes = chip->ecc.bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) void *tmp_buf = cdns_ctrl->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int i, pos, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) status = cadence_nand_select_target(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) cadence_nand_prepare_data_size(chip, TT_RAW_PAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) status = cadence_nand_cdma_transfer(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) page, cdns_ctrl->buf, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) mtd->writesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) + mtd->oobsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) 0, DMA_FROM_DEVICE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) case STAT_ERASED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) case STAT_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) dev_err(cdns_ctrl->dev, "read raw page failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* Arrange the buffer for syndrome payload/ecc layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) for (i = 0; i < ecc_steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) pos = i * (ecc_size + ecc_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) len = ecc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (pos >= writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) else if (pos + len > writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) len = writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) memcpy(buf, tmp_buf + pos, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (len < ecc_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) len = ecc_size - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) memcpy(buf, tmp_buf + writesize + oob_skip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (oob_required) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u8 *oob = chip->oob_poi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u32 oob_data_offset = (cdns_chip->sector_count - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) (cdns_chip->sector_size + chip->ecc.bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) + cdns_chip->sector_size + oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* OOB free. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) memcpy(oob, tmp_buf + oob_data_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) cdns_chip->avail_oob_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* BBM at the beginning of the OOB area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) memcpy(oob, tmp_buf + writesize, oob_skip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) oob += cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* OOB ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) for (i = 0; i < ecc_steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) pos = ecc_size + i * (ecc_size + ecc_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) len = ecc_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (i == (ecc_steps - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pos += cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (pos >= writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pos += oob_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) else if (pos + len > writesize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) len = writesize - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) memcpy(oob, tmp_buf + pos, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) oob += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (len < ecc_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) len = ecc_bytes - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) memcpy(oob, tmp_buf + writesize + oob_skip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) oob += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int cadence_nand_read_oob_raw(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return cadence_nand_read_page_raw(chip, NULL, true, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static void cadence_nand_slave_dma_transfer_finished(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct completion *finished = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) complete(finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static int cadence_nand_slave_dma_transfer(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) dma_addr_t dev_dma, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) DECLARE_COMPLETION_ONSTACK(finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct dma_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dma_addr_t src_dma, dst_dma, buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) chan = cdns_ctrl->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) dma_dev = chan->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) buf_dma = dma_map_single(dma_dev->dev, buf, len, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (dma_mapping_error(dma_dev->dev, buf_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) src_dma = cdns_ctrl->io.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) dst_dma = buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) src_dma = buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) dst_dma = cdns_ctrl->io.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) tx = dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) dev_err(cdns_ctrl->dev, "Failed to prepare DMA memcpy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) tx->callback = cadence_nand_slave_dma_transfer_finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) tx->callback_param = &finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) cookie = dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (dma_submit_error(cookie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) dev_err(cdns_ctrl->dev, "Failed to do DMA tx_submit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) dma_async_issue_pending(cdns_ctrl->dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) wait_for_completion(&finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) dev_dbg(cdns_ctrl->dev, "Fall back to CPU I/O\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) u8 thread_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) u32 sdma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* Wait until slave DMA interface is ready to data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (!cdns_ctrl->caps1->has_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) int len_in_words = len >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* read alingment data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (sdma_size > len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* read rest data from slave DMA interface if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) sdma_size / 4 - len_in_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* copy rest of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) memcpy(buf + (len_in_words << 2), cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) len - (len_in_words << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) status = cadence_nand_slave_dma_transfer(cdns_ctrl, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) cdns_ctrl->io.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dev_warn(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "Slave DMA transfer failed. Try again using bounce buffer.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* If DMA transfer is not possible or failed then use bounce buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) cdns_ctrl->io.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) sdma_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_err(cdns_ctrl->dev, "Slave DMA transfer failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) memcpy(buf, cdns_ctrl->buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) u8 thread_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) u32 sdma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* Wait until slave DMA interface is ready to data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!cdns_ctrl->caps1->has_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) int len_in_words = len >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (sdma_size > len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* copy rest of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) memcpy(cdns_ctrl->buf, buf + (len_in_words << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) len - (len_in_words << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* write all expected by nand controller data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) sdma_size / 4 - len_in_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) status = cadence_nand_slave_dma_transfer(cdns_ctrl, (void *)buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) cdns_ctrl->io.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dev_warn(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) "Slave DMA transfer failed. Try again using bounce buffer.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* If DMA transfer is not possible or failed then use bounce buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) memcpy(cdns_ctrl->buf, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) cdns_ctrl->io.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) sdma_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_err(cdns_ctrl->dev, "Slave DMA transfer failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static int cadence_nand_force_byte_access(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) bool force_8bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * Callers of this function do not verify if the NAND is using a 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * an 8-bit bus for normal operations, so we need to take care of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) * here by leaving the configuration unchanged if the NAND does not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * the NAND_BUSWIDTH_16 flag set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (!(chip->options & NAND_BUSWIDTH_16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) status = cadence_nand_set_access_width16(cdns_ctrl, !force_8bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static int cadence_nand_cmd_opcode(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) const struct nand_subop *subop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) const struct nand_op_instr *instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) unsigned int op_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) u64 mini_ctrl_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) instr = &subop->instrs[op_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (instr->delay_ns > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) mini_ctrl_cmd |= GCMD_LAY_TWB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) GCMD_LAY_INSTR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) instr->ctx.cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ret = cadence_nand_generic_cmd_send(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) mini_ctrl_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dev_err(cdns_ctrl->dev, "send cmd %x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) instr->ctx.cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static int cadence_nand_cmd_address(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) const struct nand_subop *subop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) const struct nand_op_instr *instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) unsigned int op_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) u64 mini_ctrl_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) unsigned int offset, naddrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) u64 address = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) const u8 *addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) instr = &subop->instrs[op_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if (instr->delay_ns > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) mini_ctrl_cmd |= GCMD_LAY_TWB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) GCMD_LAY_INSTR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) offset = nand_subop_get_addr_start_off(subop, op_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) addrs = &instr->ctx.addr.addrs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) for (i = 0; i < naddrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) address |= (u64)addrs[i] << (8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) naddrs - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ret = cadence_nand_generic_cmd_send(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) mini_ctrl_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dev_err(cdns_ctrl->dev, "send address %llx failed\n", address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static int cadence_nand_cmd_erase(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) const struct nand_subop *subop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) unsigned int op_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) const struct nand_op_instr *instr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) unsigned int offset, naddrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) const u8 *addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) u32 page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) instr = &subop->instrs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) offset = nand_subop_get_addr_start_off(subop, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) naddrs = nand_subop_get_num_addr_cyc(subop, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) addrs = &instr->ctx.addr.addrs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) for (i = 0; i < naddrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) page |= (u32)addrs[i] << (8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) return cadence_nand_erase(chip, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * If it is not an erase operation then handle operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * by calling exec_op function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) for (op_id = 0; op_id < subop->ninstrs; op_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) const struct nand_operation nand_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .cs = chip->cur_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .instrs = &subop->instrs[op_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .ninstrs = 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ret = chip->controller->ops->exec_op(chip, &nand_op, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static int cadence_nand_cmd_data(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) const struct nand_subop *subop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) const struct nand_op_instr *instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) unsigned int offset, op_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) u64 mini_ctrl_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) instr = &subop->instrs[op_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (instr->delay_ns > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) mini_ctrl_cmd |= GCMD_LAY_TWB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) GCMD_LAY_INSTR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (instr->type == NAND_OP_DATA_OUT_INSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) mini_ctrl_cmd |= FIELD_PREP(GCMD_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) GCMD_DIR_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) len = nand_subop_get_data_len(subop, op_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) offset = nand_subop_get_data_start_off(subop, op_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) mini_ctrl_cmd |= FIELD_PREP(GCMD_SECT_CNT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) mini_ctrl_cmd |= FIELD_PREP(GCMD_LAST_SIZE, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (instr->ctx.data.force_8bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ret = cadence_nand_force_byte_access(chip, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) "cannot change byte access generic data cmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ret = cadence_nand_generic_cmd_send(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) cdns_chip->cs[chip->cur_cs],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mini_ctrl_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_err(cdns_ctrl->dev, "send generic data cmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (instr->type == NAND_OP_DATA_IN_INSTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) void *buf = instr->ctx.data.buf.in + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ret = cadence_nand_read_buf(cdns_ctrl, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) const void *buf = instr->ctx.data.buf.out + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ret = cadence_nand_write_buf(cdns_ctrl, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) dev_err(cdns_ctrl->dev, "data transfer failed for generic command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (instr->ctx.data.force_8bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ret = cadence_nand_force_byte_access(chip, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) "cannot change byte access generic data cmd failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static int cadence_nand_cmd_waitrdy(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) const struct nand_subop *subop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) unsigned int op_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) const struct nand_op_instr *instr = &subop->instrs[op_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) u32 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) status = cadence_nand_wait_for_value(cdns_ctrl, RBN_SETINGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) timeout_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) BIT(cdns_chip->cs[chip->cur_cs]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static const struct nand_op_parser cadence_nand_op_parser = NAND_OP_PARSER(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) cadence_nand_cmd_erase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) NAND_OP_PARSER_PAT_CMD_ELEM(false),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ERASE_ADDRESS_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) NAND_OP_PARSER_PAT_CMD_ELEM(false),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) cadence_nand_cmd_opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) NAND_OP_PARSER_PAT_CMD_ELEM(false)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) cadence_nand_cmd_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) cadence_nand_cmd_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_DATA_SIZE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) cadence_nand_cmd_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) NAND_OP_PARSER_PATTERN(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) cadence_nand_cmd_waitrdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) NAND_OP_PARSER_PAT_WAITRDY_ELEM(false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static int cadence_nand_exec_op(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) const struct nand_operation *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) bool check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (!check_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) int status = cadence_nand_select_target(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return nand_op_parser_exec_op(chip, &cadence_nand_op_parser, op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) check_only);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static int cadence_nand_ooblayout_free(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) struct nand_chip *chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) oobregion->offset = cdns_chip->bbm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) oobregion->length = cdns_chip->avail_oob_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) - cdns_chip->bbm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static int cadence_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) struct nand_chip *chip = mtd_to_nand(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) oobregion->offset = cdns_chip->avail_oob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) oobregion->length = chip->ecc.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static const struct mtd_ooblayout_ops cadence_nand_ooblayout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .free = cadence_nand_ooblayout_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .ecc = cadence_nand_ooblayout_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static int calc_cycl(u32 timing, u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (timing == 0 || clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if ((timing % clock) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) return timing / clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return timing / clock - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /* Calculate max data valid window. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) u32 board_delay_skew_min, u32 ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (ext_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) clk_period /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) return (trp_cnt + 1) * clk_period + trhoh_min +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) board_delay_skew_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* Calculate data valid window. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) u32 trea_max, u32 ext_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (ext_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) clk_period /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) return (trp_cnt + 1) * clk_period + trhoh_min - trea_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) const struct nand_interface_config *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) const struct nand_sdr_timings *sdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) struct cadence_nand_timings *t = &cdns_chip->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) u32 board_delay = cdns_ctrl->board_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) cdns_ctrl->nf_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) u32 tfeat_cnt, trhz_cnt, tvdly_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) u32 trhw_cnt, twb_cnt, twh_cnt = 0, twhr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) u32 twp_cnt = 0, trp_cnt = 0, trh_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) u32 if_skew = cdns_ctrl->caps1->if_skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) u32 board_delay_skew_min = board_delay - if_skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) u32 board_delay_skew_max = board_delay + if_skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) u32 dqs_sampl_res, phony_dqs_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) u32 tdvw, tdvw_min, tdvw_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) u32 ext_rd_mode, ext_wr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) u32 sampling_point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) sdr = nand_get_sdr_timings(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) if (IS_ERR(sdr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) return PTR_ERR(sdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) memset(t, 0, sizeof(*t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /* Sampling point calculation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (cdns_ctrl->caps2.is_phy_type_dll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) phony_dqs_mod = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) phony_dqs_mod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) dqs_sampl_res = clk_period / phony_dqs_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) tdvw_min = sdr->tREA_max + board_delay_skew_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) * The idea of those calculation is to get the optimum value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * for tRP and tRH timings. If it is NOT possible to sample data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) * with optimal tRP/tRH settings, the parameters will be extended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) * If clk_period is 50ns (the lowest value) this condition is met
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) * for asynchronous timing modes 1, 2, 3, 4 and 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) * If clk_period is 20ns the condition is met only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) * for asynchronous timing mode 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (sdr->tRC_min <= clk_period &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) sdr->tRP_min <= (clk_period / 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) sdr->tREH_min <= (clk_period / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* Performance mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ext_rd_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) sdr->tREA_max, ext_rd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) board_delay_skew_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ext_rd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * Check if data valid window and sampling point can be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) * and is not on the edge (ie. we have hold margin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) * If not extend the tRP timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (tdvw > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (tdvw_max <= tdvw_min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) (tdvw_max % dqs_sampl_res) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * No valid sampling point so the RE pulse need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) * to be widen widening by half clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ext_rd_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) * There is no valid window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) * to be able to sample data the tRP need to be widen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) * Very safe calculations are performed here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) trp_cnt = (sdr->tREA_max + board_delay_skew_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) + dqs_sampl_res) / clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ext_rd_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* Extended read mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) u32 trh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ext_rd_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) trp_cnt = calc_cycl(sdr->tRP_min, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (sdr->tREH_min >= trh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) trh_cnt = calc_cycl(sdr->tREH_min, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) trh_cnt = calc_cycl(trh, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) sdr->tREA_max, ext_rd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) * Check if data valid window and sampling point can be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) * or if it is at the edge check if previous is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) * - if not extend the tRP timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (tdvw > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) sdr->tRHOH_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) board_delay_skew_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) ext_rd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if ((((tdvw_max / dqs_sampl_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) * dqs_sampl_res) <= tdvw_min) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) (((tdvw_max % dqs_sampl_res) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) (((tdvw_max / dqs_sampl_res - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) * dqs_sampl_res) <= tdvw_min))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) * Data valid window width is lower than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) * sampling resolution and do not hit any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * sampling point to be sure the sampling point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) * will be found the RE low pulse width will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * extended by one clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) trp_cnt = trp_cnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * There is no valid window to be able to sample data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * The tRP need to be widen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * Very safe calculations are performed here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) trp_cnt = (sdr->tREA_max + board_delay_skew_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) + dqs_sampl_res) / clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) sdr->tRHOH_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) board_delay_skew_min, ext_rd_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (sdr->tWC_min <= clk_period &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) (sdr->tWP_min + if_skew) <= (clk_period / 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) (sdr->tWH_min + if_skew) <= (clk_period / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ext_wr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 twh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ext_wr_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) twp_cnt = calc_cycl(sdr->tALS_min + if_skew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (sdr->tWH_min >= twh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) twh = sdr->tWH_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) twh_cnt = calc_cycl(twh + if_skew, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) reg = FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRH, trh_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRP, trp_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWH, twh_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWP, twp_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) t->async_toggle_timings = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) dev_dbg(cdns_ctrl->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) * If timing exceeds delay field in timing register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * then use maximum value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) if (FIELD_FIT(TIMINGS0_TCCS, tccs_cnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) reg |= TIMINGS0_TCCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) t->timings0 = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) dev_dbg(cdns_ctrl->dev, "TIMINGS0_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* The following is related to single signal so skew is not needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) trhz_cnt = trhz_cnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) * Because of the two stage syncflop the value must be increased by 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) * first value is related with sync, second value is related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) * with output if delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) twb_cnt = twb_cnt + 3 + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * The following is related to the we edge of the random data input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) * sequence so skew is not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) tvdly_cnt = calc_cycl(500000 + if_skew, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) reg = FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) reg |= FIELD_PREP(TIMINGS1_TWB, twb_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) t->timings1 = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) dev_dbg(cdns_ctrl->dev, "TIMINGS1_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (tfeat_cnt < twb_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) tfeat_cnt = twb_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) t->timings2 = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) dev_dbg(cdns_ctrl->dev, "TIMINGS2_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) if (cdns_ctrl->caps2.is_phy_type_dll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) reg = DLL_PHY_CTRL_DLL_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (ext_wr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) reg |= DLL_PHY_CTRL_EXTENDED_WR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (ext_rd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) reg |= DLL_PHY_CTRL_EXTENDED_RD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) reg |= FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) t->dll_phy_ctrl = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) /* Sampling point calculation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if ((tdvw_max % dqs_sampl_res) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) sampling_point = tdvw_max / dqs_sampl_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) sampling_point = (tdvw_max / dqs_sampl_res - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (sampling_point * dqs_sampl_res > tdvw_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dll_phy_dqs_timing =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) dll_phy_dqs_timing |= PHY_DQS_TIMING_USE_PHONY_DQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) phony_dqs_timing = sampling_point / phony_dqs_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if ((sampling_point % 2) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) dll_phy_dqs_timing |= PHY_DQS_TIMING_PHONY_DQS_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if ((tdvw_max % dqs_sampl_res) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * Calculation for sampling point at the edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) * of data and being odd number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) phony_dqs_timing = (tdvw_max / dqs_sampl_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) / phony_dqs_mod - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (!cdns_ctrl->caps2.is_phy_type_dll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) phony_dqs_timing--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) phony_dqs_timing--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) rd_del_sel = phony_dqs_timing + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) dev_warn(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) "ERROR : cannot find valid sampling point\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) reg = FIELD_PREP(PHY_CTRL_PHONY_DQS, phony_dqs_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (cdns_ctrl->caps2.is_phy_type_dll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) reg |= PHY_CTRL_SDR_DQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) t->phy_ctrl = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_SDR\t%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) if (cdns_ctrl->caps2.is_phy_type_dll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) dev_dbg(cdns_ctrl->dev, "PHY_TSEL_REG_SDR\t%x\n", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) dll_phy_dqs_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) t->phy_dqs_timing = dll_phy_dqs_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) t->phy_gate_lpbk_ctrl = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) dev_dbg(cdns_ctrl->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) PHY_DLL_MASTER_CTRL_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static int cadence_nand_attach_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) u32 ecc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) struct mtd_info *mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (chip->options & NAND_BUSWIDTH_16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ret = cadence_nand_set_access_width16(cdns_ctrl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) chip->bbt_options |= NAND_BBT_USE_FLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) chip->bbt_options |= NAND_BBT_NO_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) chip->options |= NAND_NO_SUBPAGE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) cdns_chip->bbm_offs = chip->badblockpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) cdns_chip->bbm_offs &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /* this value should be even number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) cdns_chip->bbm_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) ret = nand_ecc_choose_conf(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) &cdns_ctrl->ecc_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) mtd->oobsize - cdns_chip->bbm_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) dev_err(cdns_ctrl->dev, "ECC configuration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) dev_dbg(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* Error correction configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) cdns_chip->sector_size = chip->ecc.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) > mtd->oobsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) cdns_chip->avail_oob_size -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) ret = cadence_nand_get_ecc_strength_idx(cdns_ctrl, chip->ecc.strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) cdns_chip->corr_str_idx = (u8)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) CTRL_STATUS_CTRL_BUSY, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) cadence_nand_set_ecc_strength(cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) cdns_chip->corr_str_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) cadence_nand_set_erase_detection(cdns_ctrl, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) chip->ecc.strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) /* Override the default read operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) chip->ecc.read_page = cadence_nand_read_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) chip->ecc.read_page_raw = cadence_nand_read_page_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) chip->ecc.write_page = cadence_nand_write_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) chip->ecc.write_page_raw = cadence_nand_write_page_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) chip->ecc.read_oob = cadence_nand_read_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) chip->ecc.write_oob = cadence_nand_write_oob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) if ((mtd->writesize + mtd->oobsize) > cdns_ctrl->buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) cdns_ctrl->buf_size = mtd->writesize + mtd->oobsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* Is 32-bit DMA supported? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ret = dma_set_mask(cdns_ctrl->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) dev_err(cdns_ctrl->dev, "no usable DMA configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static const struct nand_controller_ops cadence_nand_controller_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .attach_chip = cadence_nand_attach_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .exec_op = cadence_nand_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .setup_interface = cadence_nand_setup_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static int cadence_nand_chip_init(struct cdns_nand_ctrl *cdns_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) struct cdns_nand_chip *cdns_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) struct nand_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) int nsels, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (nsels <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) dev_err(cdns_ctrl->dev, "missing/invalid reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) /* Allocate the nand chip structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) cdns_chip = devm_kzalloc(cdns_ctrl->dev, sizeof(*cdns_chip) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) (nsels * sizeof(u8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (!cdns_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) dev_err(cdns_ctrl->dev, "could not allocate chip structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) cdns_chip->nsels = nsels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) for (i = 0; i < nsels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* Retrieve CS id. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) ret = of_property_read_u32_index(np, "reg", i, &cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) "could not retrieve reg property: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (cs >= cdns_ctrl->caps2.max_banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) "invalid reg value: %u (max CS = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) cs, cdns_ctrl->caps2.max_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) if (test_and_set_bit(cs, &cdns_ctrl->assigned_cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) "CS %d already assigned\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) cdns_chip->cs[i] = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) chip = &cdns_chip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) chip->controller = &cdns_ctrl->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) nand_set_flash_node(chip, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) mtd = nand_to_mtd(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) mtd->dev.parent = cdns_ctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) * Default to HW ECC engine mode. If the nand-ecc-mode property is given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) * in the DT node, this entry will be overwritten in nand_scan_ident().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) ret = nand_scan(chip, cdns_chip->nsels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) dev_err(cdns_ctrl->dev, "could not scan the nand chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) ret = mtd_device_register(mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) "failed to register mtd device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) list_add_tail(&cdns_chip->node, &cdns_ctrl->chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static void cadence_nand_chips_cleanup(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) struct cdns_nand_chip *entry, *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) struct nand_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) list_for_each_entry_safe(entry, temp, &cdns_ctrl->chips, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) chip = &entry->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) ret = mtd_device_unregister(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) list_del(&entry->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static int cadence_nand_chips_init(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) struct device_node *np = cdns_ctrl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) struct device_node *nand_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) int max_cs = cdns_ctrl->caps2.max_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) int nchips, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) nchips = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) if (nchips > max_cs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) "too many NAND chips: %d (max = %d CS)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) nchips, max_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) for_each_child_of_node(np, nand_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ret = cadence_nand_chip_init(cdns_ctrl, nand_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) of_node_put(nand_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) cadence_nand_chips_cleanup(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) cadence_nand_irq_cleanup(int irqnum, struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) static int cadence_nand_init(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) cdns_ctrl->cdma_desc = dma_alloc_coherent(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) sizeof(*cdns_ctrl->cdma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) &cdns_ctrl->dma_cdma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) if (!cdns_ctrl->dma_cdma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) cdns_ctrl->buf_size = SZ_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) cdns_ctrl->buf = kmalloc(cdns_ctrl->buf_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (!cdns_ctrl->buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) goto free_buf_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) if (devm_request_irq(cdns_ctrl->dev, cdns_ctrl->irq, cadence_nand_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) IRQF_SHARED, "cadence-nand-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) cdns_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) dev_err(cdns_ctrl->dev, "Unable to allocate IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) goto free_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) spin_lock_init(&cdns_ctrl->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) init_completion(&cdns_ctrl->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) ret = cadence_nand_hw_init(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) goto disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) dma_cap_set(DMA_MEMCPY, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) if (cdns_ctrl->caps1->has_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) cdns_ctrl->dmac = dma_request_channel(mask, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) if (!cdns_ctrl->dmac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) dev_err(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) "Unable to get a DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) goto disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) nand_controller_init(&cdns_ctrl->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) INIT_LIST_HEAD(&cdns_ctrl->chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) cdns_ctrl->controller.ops = &cadence_nand_controller_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) cdns_ctrl->curr_corr_str_idx = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) ret = cadence_nand_chips_init(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) goto dma_release_chnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) kfree(cdns_ctrl->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) cdns_ctrl->buf = kzalloc(cdns_ctrl->buf_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) if (!cdns_ctrl->buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) goto dma_release_chnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) dma_release_chnl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) if (cdns_ctrl->dmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) dma_release_channel(cdns_ctrl->dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) disable_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) free_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) kfree(cdns_ctrl->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) free_buf_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) /* Driver exit point. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static void cadence_nand_remove(struct cdns_nand_ctrl *cdns_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) cadence_nand_chips_cleanup(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) kfree(cdns_ctrl->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) if (cdns_ctrl->dmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) dma_release_channel(cdns_ctrl->dmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) struct cadence_nand_dt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) struct cdns_nand_ctrl cdns_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) static const struct cadence_nand_dt_devdata cadence_nand_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .if_skew = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .has_dma = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) static const struct of_device_id cadence_nand_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .compatible = "cdns,hp-nfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .data = &cadence_nand_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) MODULE_DEVICE_TABLE(of, cadence_nand_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static int cadence_nand_dt_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) struct cadence_nand_dt *dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) struct cdns_nand_ctrl *cdns_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) const struct cadence_nand_dt_devdata *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) of_id = of_match_device(cadence_nand_dt_ids, &ofdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) ofdev->id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) devdata = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) pr_err("Failed to find the right device id.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) dt = devm_kzalloc(&ofdev->dev, sizeof(*dt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if (!dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) cdns_ctrl = &dt->cdns_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) cdns_ctrl->caps1 = devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) cdns_ctrl->dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) cdns_ctrl->irq = platform_get_irq(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (cdns_ctrl->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) return cdns_ctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) dev_info(cdns_ctrl->dev, "IRQ: nr %d\n", cdns_ctrl->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) cdns_ctrl->reg = devm_platform_ioremap_resource(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) if (IS_ERR(cdns_ctrl->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) return PTR_ERR(cdns_ctrl->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) cdns_ctrl->io.dma = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) cdns_ctrl->io.virt = devm_ioremap_resource(&ofdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) if (IS_ERR(cdns_ctrl->io.virt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) return PTR_ERR(cdns_ctrl->io.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) dt->clk = devm_clk_get(cdns_ctrl->dev, "nf_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) if (IS_ERR(dt->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return PTR_ERR(dt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) cdns_ctrl->nf_clk_rate = clk_get_rate(dt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ret = of_property_read_u32(ofdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) "cdns,board-delay-ps", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) val = 4830;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) dev_info(cdns_ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) "missing cdns,board-delay-ps property, %d was set\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) cdns_ctrl->board_delay = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) ret = cadence_nand_init(cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) platform_set_drvdata(ofdev, dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static int cadence_nand_dt_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) struct cadence_nand_dt *dt = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) cadence_nand_remove(&dt->cdns_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static struct platform_driver cadence_nand_dt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .probe = cadence_nand_dt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .remove = cadence_nand_dt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .name = "cadence-nand-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .of_match_table = cadence_nand_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) module_platform_driver(cadence_nand_dt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) MODULE_AUTHOR("Piotr Sroka <piotrs@cadence.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) MODULE_DESCRIPTION("Driver for Cadence NAND flash controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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