^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004 Embedded Edge, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach-au1x00/au1000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach-au1x00/au1550nd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct au1550nd_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct nand_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct nand_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return container_of(this, struct au1550nd_ctx, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * au_write_buf - write buffer to chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @this: NAND chip object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @len: number of bytes to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * write function for 8bit buswidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void au_write_buf(struct nand_chip *this, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const u8 *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writeb(p[i], ctx->base + MEM_STNAND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * au_read_buf - read chip data into buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @this: NAND chip object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @buf: buffer to store date
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @len: number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * read function for 8bit buswidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void au_read_buf(struct nand_chip *this, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) p[i] = readb(ctx->base + MEM_STNAND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * au_write_buf16 - write buffer to chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @this: NAND chip object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @len: number of bytes to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * write function for 16bit buswidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void au_write_buf16(struct nand_chip *this, const void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const u16 *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) len >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writew(p[i], ctx->base + MEM_STNAND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * au_read_buf16 - read chip data into buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @this: NAND chip object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @buf: buffer to store date
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @len: number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * read function for 16bit buswidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void au_read_buf16(struct nand_chip *this, void *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) len >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) p[i] = readw(ctx->base + MEM_STNAND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) wmb(); /* drain writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int find_nand_cs(unsigned long nand_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long addr, staddr, start, mask, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) addr = 0x1000 + (i * 0x10); /* CSx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* figure out the decoded range of this CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) start = (staddr << 4) & 0xfffc0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mask = (staddr << 18) & 0xfffc0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) end = (start | (start - 1)) & ~(start ^ mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((nand_base >= start) && (nand_base < end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int au1550nd_waitrdy(struct nand_chip *this, unsigned int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long timeout_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) timeout_jiffies += msecs_to_jiffies(timeout_ms) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } while (time_before(jiffies, timeout_jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int au1550nd_exec_instr(struct nand_chip *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct nand_op_instr *instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (instr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case NAND_OP_CMD_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writeb(instr->ctx.cmd.opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ctx->base + MEM_STNAND_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Drain the writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case NAND_OP_ADDR_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < instr->ctx.addr.naddrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writeb(instr->ctx.addr.addrs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ctx->base + MEM_STNAND_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Drain the writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case NAND_OP_DATA_IN_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if ((this->options & NAND_BUSWIDTH_16) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) !instr->ctx.data.force_8bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) au_read_buf16(this, instr->ctx.data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) au_read_buf(this, instr->ctx.data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case NAND_OP_DATA_OUT_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if ((this->options & NAND_BUSWIDTH_16) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) !instr->ctx.data.force_8bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) au_write_buf16(this, instr->ctx.data.buf.out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) au_write_buf(this, instr->ctx.data.buf.out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case NAND_OP_WAITRDY_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = au1550nd_waitrdy(this, instr->ctx.waitrdy.timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (instr->delay_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ndelay(instr->delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int au1550nd_exec_op(struct nand_chip *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct nand_operation *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct au1550nd_ctx *ctx = chip_to_au_ctx(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* assert (force assert) chip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Drain the writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; i < op->ninstrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = au1550nd_exec_instr(this, &op->instrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* deassert chip enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Drain the writebuffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int au1550nd_attach_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct nand_controller_ops au1550nd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .exec_op = au1550nd_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .attach_chip = au1550nd_attach_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int au1550nd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct au1550nd_platdata *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct au1550nd_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct nand_chip *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret, cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pd = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_err(&pdev->dev, "missing platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(&pdev->dev, "no NAND memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(&pdev->dev, "cannot claim NAND memory area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ctx->base = ioremap(r->start, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!ctx->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(&pdev->dev, "cannot remap NAND memory area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) this = &ctx->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mtd = nand_to_mtd(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mtd->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* figure out which CS# r->start belongs to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cs = find_nand_cs(r->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (cs < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ctx->cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) nand_controller_init(&ctx->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ctx->controller.ops = &au1550nd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) this->controller = &ctx->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (pd->devwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) this->options |= NAND_BUSWIDTH_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * This driver assumes that the default ECC engine should be TYPE_SOFT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Set ->engine_type before registering the NAND devices in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * provide a driver specific default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = nand_scan(this, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mtd_device_register(mtd, pd->parts, pd->num_parts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) out3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) iounmap(ctx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) release_mem_region(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int au1550nd_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct nand_chip *chip = &ctx->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = mtd_device_unregister(nand_to_mtd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) nand_cleanup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) iounmap(ctx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) release_mem_region(r->start, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct platform_driver au1550nd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "au1550-nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .probe = au1550nd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .remove = au1550nd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_platform_driver(au1550nd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_AUTHOR("Embedded Edge, LLC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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