Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *    Copyright (c) 2003 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *    Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Partially stolen from plat_nand.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Overview:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   This is a device driver for the NAND flash device found on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *   Amstrad E3 (Delta).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mtd/nand-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * MTD structure for E3 (Delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct gpio_nand {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct nand_controller	base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct nand_chip	nand_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct gpio_desc	*gpiod_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct gpio_desc	*gpiod_nce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct gpio_desc	*gpiod_nre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct gpio_desc	*gpiod_nwp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct gpio_desc	*gpiod_nwe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct gpio_desc	*gpiod_ale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct gpio_desc	*gpiod_cle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct gpio_descs	*data_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	bool			data_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int		tRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int		tWP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u8			(*io_read)(struct gpio_nand *this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	void			(*io_write)(struct gpio_nand *this, u8 byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void gpio_nand_write_commit(struct gpio_nand *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	gpiod_set_value(priv->gpiod_nwe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ndelay(priv->tWP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	gpiod_set_value(priv->gpiod_nwe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void gpio_nand_io_write(struct gpio_nand *priv, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct gpio_descs *data_gpiods = priv->data_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				  data_gpiods->info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	gpio_nand_write_commit(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void gpio_nand_dir_output(struct gpio_nand *priv, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct gpio_descs *data_gpiods = priv->data_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	for (i = 0; i < data_gpiods->ndescs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		gpiod_direction_output_raw(data_gpiods->desc[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					   test_bit(i, values));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	gpio_nand_write_commit(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	priv->data_in = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static u8 gpio_nand_io_read(struct gpio_nand *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct gpio_descs *data_gpiods = priv->data_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DECLARE_BITMAP(values, BITS_PER_TYPE(res)) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	gpiod_set_value(priv->gpiod_nre, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ndelay(priv->tRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	gpiod_get_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				  data_gpiods->info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	gpiod_set_value(priv->gpiod_nre, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	res = values[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void gpio_nand_dir_input(struct gpio_nand *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct gpio_descs *data_gpiods = priv->data_gpiods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	for (i = 0; i < data_gpiods->ndescs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		gpiod_direction_input(data_gpiods->desc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	priv->data_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void gpio_nand_write_buf(struct gpio_nand *priv, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (len > 0 && priv->data_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		gpio_nand_dir_output(priv, buf[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	while (i < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		priv->io_write(priv, buf[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void gpio_nand_read_buf(struct gpio_nand *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (priv->data_gpiods && !priv->data_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		gpio_nand_dir_input(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		buf[i] = priv->io_read(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void gpio_nand_ctrl_cs(struct gpio_nand *priv, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	gpiod_set_value(priv->gpiod_nce, assert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int gpio_nand_exec_op(struct nand_chip *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			     const struct nand_operation *op, bool check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct gpio_nand *priv = nand_get_controller_data(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	const struct nand_op_instr *instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (check_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	gpio_nand_ctrl_cs(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		switch (instr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case NAND_OP_CMD_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			gpiod_set_value(priv->gpiod_cle, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			gpio_nand_write_buf(priv, &instr->ctx.cmd.opcode, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			gpiod_set_value(priv->gpiod_cle, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		case NAND_OP_ADDR_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			gpiod_set_value(priv->gpiod_ale, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			gpio_nand_write_buf(priv, instr->ctx.addr.addrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					    instr->ctx.addr.naddrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			gpiod_set_value(priv->gpiod_ale, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		case NAND_OP_DATA_IN_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			gpio_nand_read_buf(priv, instr->ctx.data.buf.in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					   instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		case NAND_OP_DATA_OUT_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			gpio_nand_write_buf(priv, instr->ctx.data.buf.out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 					    instr->ctx.data.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		case NAND_OP_WAITRDY_INSTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			ret = priv->gpiod_rdy ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			      nand_gpio_waitrdy(this, priv->gpiod_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 						instr->ctx.waitrdy.timeout_ms) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			      nand_soft_waitrdy(this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 						instr->ctx.waitrdy.timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	gpio_nand_ctrl_cs(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int gpio_nand_setup_interface(struct nand_chip *this, int csline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				     const struct nand_interface_config *cf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct gpio_nand *priv = nand_get_controller_data(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct device *dev = &nand_to_mtd(this)->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (IS_ERR(sdr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return PTR_ERR(sdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (csline == NAND_DATA_IFACE_CHECK_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (priv->gpiod_nre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	dev_dbg(dev, "using %u ns write pulse width\n", priv->tWP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int gpio_nand_attach_chip(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct nand_controller_ops gpio_nand_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.exec_op = gpio_nand_exec_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.attach_chip = gpio_nand_attach_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.setup_interface = gpio_nand_setup_interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * Main initialization routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int gpio_nand_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct gpio_nand_platdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	const struct mtd_partition *partitions = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int num_partitions = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct gpio_nand *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct nand_chip *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int (*probe)(struct platform_device *pdev, struct gpio_nand *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		partitions = pdata->parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		num_partitions = pdata->num_parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Allocate memory for MTD device structure and private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	priv = devm_kzalloc(&pdev->dev, sizeof(struct gpio_nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	this = &priv->nand_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	mtd = nand_to_mtd(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mtd->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	nand_set_controller_data(this, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	nand_set_flash_node(this, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (IS_ERR(priv->gpiod_rdy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		err = PTR_ERR(priv->gpiod_rdy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Set chip enabled but write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	priv->gpiod_nwp = devm_gpiod_get_optional(&pdev->dev, "nwp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 						  GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (IS_ERR(priv->gpiod_nwp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		err = PTR_ERR(priv->gpiod_nwp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	priv->gpiod_nce = devm_gpiod_get_optional(&pdev->dev, "nce",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 						  GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (IS_ERR(priv->gpiod_nce)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		err = PTR_ERR(priv->gpiod_nce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	priv->gpiod_nre = devm_gpiod_get_optional(&pdev->dev, "nre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						  GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (IS_ERR(priv->gpiod_nre)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		err = PTR_ERR(priv->gpiod_nre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	priv->gpiod_nwe = devm_gpiod_get_optional(&pdev->dev, "nwe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 						  GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (IS_ERR(priv->gpiod_nwe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		err = PTR_ERR(priv->gpiod_nwe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	priv->gpiod_ale = devm_gpiod_get(&pdev->dev, "ale", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (IS_ERR(priv->gpiod_ale)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		err = PTR_ERR(priv->gpiod_ale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		dev_err(&pdev->dev, "ALE GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	priv->gpiod_cle = devm_gpiod_get(&pdev->dev, "cle", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (IS_ERR(priv->gpiod_cle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		err = PTR_ERR(priv->gpiod_cle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		dev_err(&pdev->dev, "CLE GPIO request failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	/* Request array of data pins, initialize them as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	priv->data_gpiods = devm_gpiod_get_array_optional(&pdev->dev, "data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 							  GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (IS_ERR(priv->data_gpiods)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		err = PTR_ERR(priv->data_gpiods);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		dev_err(&pdev->dev, "data GPIO request failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (priv->data_gpiods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		if (!priv->gpiod_nwe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				"mandatory NWE pin not provided by platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		priv->io_read = gpio_nand_io_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		priv->io_write = gpio_nand_io_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		priv->data_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (pdev->id_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		probe = (void *) pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		probe = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		err = probe(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (!priv->io_read || !priv->io_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		dev_err(&pdev->dev, "incomplete device configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Initialize the NAND controller object embedded in gpio_nand. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	priv->base.ops = &gpio_nand_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	nand_controller_init(&priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	this->controller = &priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 * FIXME: We should release write protection only after nand_scan() to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 * be on the safe side but we can't do that until we have a generic way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	 * to assert/deassert WP from the core.  Even if the core shouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	 * write things in the nand_scan() path, it should have control on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * pin just in case we ever need to disable write protection during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * chip detection/initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/* Release write protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	gpiod_set_value(priv->gpiod_nwp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 * This driver assumes that the default ECC engine should be TYPE_SOFT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * Set ->engine_type before registering the NAND devices in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 * provide a driver specific default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* Scan to find existence of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	err = nand_scan(this, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* Register the partitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	err = mtd_device_register(mtd, partitions, num_partitions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		goto err_nand_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) err_nand_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	nand_cleanup(this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  * Clean up routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int gpio_nand_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct gpio_nand *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* Apply write protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	gpiod_set_value(priv->gpiod_nwp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* Unregister device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ret = mtd_device_unregister(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	WARN_ON(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	nand_cleanup(mtd_to_nand(mtd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct of_device_id gpio_nand_of_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MODULE_DEVICE_TABLE(of, gpio_nand_of_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct platform_device_id gpio_nand_plat_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.name	= "ams-delta-nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_DEVICE_TABLE(platform, gpio_nand_plat_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct platform_driver gpio_nand_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.probe		= gpio_nand_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.remove		= gpio_nand_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.id_table	= gpio_nand_plat_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.name	= "ams-delta-nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.of_match_table = of_match_ptr(gpio_nand_of_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_platform_driver(gpio_nand_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");