Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) config MTD_NAND_ECC_SW_HAMMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 	tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) config MTD_NAND_ECC_SW_HAMMING_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	bool "NAND ECC Smart Media byte order"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	depends on MTD_NAND_ECC_SW_HAMMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	  Software ECC according to the Smart Media Specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	  The original Linux implementation had byte 0 and 1 swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) menuconfig MTD_RAW_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	tristate "Raw/Parallel NAND Device Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	select MTD_NAND_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	select MTD_NAND_ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	select MTD_NAND_ECC_SW_HAMMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	  This enables support for accessing all type of raw/parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	  NAND flash devices. For further information see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	  <http://www.linux-mtd.infradead.org/doc/nand.html>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) if MTD_RAW_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) config MTD_NAND_ECC_SW_BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	bool "Support software BCH ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	select BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	  This enables support for software BCH error correction. Binary BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	  codes are more powerful and cpu intensive than traditional Hamming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	  ECC codes. They are used with NAND devices requiring more than 1 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	  of error correction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) comment "Raw/parallel NAND flash controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) config MTD_NAND_DENALI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) config MTD_NAND_DENALI_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	tristate "Denali NAND controller on Intel Moorestown"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	select MTD_NAND_DENALI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	  Enable the driver for NAND flash on Intel Moorestown, using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  Denali NAND controller core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) config MTD_NAND_DENALI_DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	tristate "Denali NAND controller as a DT device"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	select MTD_NAND_DENALI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	depends on HAS_DMA && HAVE_CLK && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  Enable the driver for NAND flash on platforms using a Denali NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	  controller as a DT device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) config MTD_NAND_AMS_DELTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	tristate "Amstrad E3 NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	depends on MACH_AMS_DELTA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	  Support for NAND flash on Amstrad E3 (Delta).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) config MTD_NAND_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	  Support for NAND flash on Texas Instruments OMAP2, OMAP3, OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	  and Keystone platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) config MTD_NAND_OMAP_BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	depends on MTD_NAND_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	bool "Support hardware based BCH error correction"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	select BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	  This config enables the ELM hardware engine, which can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	  locate and correct errors when using BCH ECC scheme. This offloads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	  the cpu from doing ECC error searching and correction. However some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	  legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	  so this is optional for them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) config MTD_NAND_OMAP_BCH_BUILD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	def_tristate MTD_NAND_OMAP2 && MTD_NAND_OMAP_BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) config MTD_NAND_AU1550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tristate "Au1550/1200 NAND support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	depends on MIPS_ALCHEMY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	  This enables the driver for the NAND flash controller on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	  AMD/Alchemy 1550 SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) config MTD_NAND_NDFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	tristate "IBM/MCC 4xx NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	depends on 4xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	select MTD_NAND_ECC_SW_HAMMING_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	  NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) config MTD_NAND_S3C2410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	tristate "Samsung S3C NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	depends on ARCH_S3C24XX || ARCH_S3C64XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  This enables the NAND flash controller on the S3C24xx and S3C64xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	  SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	  No board specific support is done by this driver, each board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	  must advertise a platform_device for the driver to attach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) config MTD_NAND_S3C2410_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bool "Samsung S3C NAND controller debug"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	depends on MTD_NAND_S3C2410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  Enable debugging of the S3C NAND driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) config MTD_NAND_S3C2410_CLKSTOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	bool "Samsung S3C NAND IDLE clock stop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	depends on MTD_NAND_S3C2410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	  Stop the clock to the NAND controller when there is no chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	  selected to save power. This will mean there is a small delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	  when the is NAND chip selected or released, but will save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	  approximately 5mA of power when there is nothing happening.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) config MTD_NAND_TANGO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	tristate "Tango NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	depends on ARCH_TANGO || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	  Enables the NAND Flash controller on Tango chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) config MTD_NAND_SHARPSL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	tristate "Sharp SL Series (C7xx + others) NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	depends on ARCH_PXA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) config MTD_NAND_CAFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	tristate "OLPC CAFÉ NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	select REED_SOLOMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	select REED_SOLOMON_DEC16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	  Use NAND flash attached to the CAFÉ chip designed for the OLPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	  laptop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) config MTD_NAND_CS553X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	tristate "CS5535/CS5536 (AMD Geode companion) NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	depends on X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	depends on !UML && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	  The CS553x companion chips for the AMD Geode processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	  include NAND flash controllers with built-in hardware ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	  capabilities; enabling this option will allow you to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	  these. The driver will check the MSRs to verify that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	  controller is enabled for NAND, and currently requires that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	  the controller be in MMIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	  If you say "m", the module will be called cs553x_nand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) config MTD_NAND_ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	tristate "Atmel AT91 NAND Flash/SmartMedia NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	depends on ARCH_AT91 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	select GENERIC_ALLOCATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	select MFD_ATMEL_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	  Enables support for NAND Flash / Smart Media Card interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	  on Atmel AT91 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) config MTD_NAND_ORION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	tristate "Marvell Orion NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	depends on PLAT_ORION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	  This enables the NAND flash controller on Orion machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	  No board specific support is done by this driver, each board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	  must advertise a platform_device for the driver to attach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config MTD_NAND_MARVELL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	tristate "Marvell EBU NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_MVEBU || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		   COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	  This enables the NAND flash controller driver for Marvell boards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	  including:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	  - PXA3xx processors (NFCv1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	  - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	  - 64-bit Aramda platforms (7k, 8k) (NFCv2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) config MTD_NAND_SLC_LPC32XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tristate "NXP LPC32xx SLC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	depends on ARCH_LPC32XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	  Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	  chips) NAND controller. This is the default for the PHYTEC 3250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	  reference board which contains a NAND256R3A2CZA6 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	  Please check the actual NAND chip connected and its support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	  by the SLC NAND controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) config MTD_NAND_MLC_LPC32XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	tristate "NXP LPC32xx MLC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	depends on ARCH_LPC32XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	  Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	  controller. This is the default for the WORK92105 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	  board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	  Please check the actual NAND chip connected and its support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	  by the MLC NAND controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) config MTD_NAND_PASEMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	tristate "PA Semi PWRficient NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	depends on PPC_PASEMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	  Enables support for NAND Flash interface on PA Semi PWRficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	  based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) config MTD_NAND_TMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	tristate "Toshiba Mobile IO NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	depends on MFD_TMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	  Support for NAND flash connected to a Toshiba Mobile IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	  Controller in some PDAs, including the Sharp SL6000x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) config MTD_NAND_BRCMNAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	tristate "Broadcom STB NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	depends on ARM || ARM64 || MIPS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	  Enables the Broadcom NAND controller driver. The controller was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	  originally designed for Set-Top Box but is used on various BCM7xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	  BCM3xxx, BCM63xxx, iProc/Cygnus and more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) config MTD_NAND_BCM47XXNFLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	tristate "BCM4706 BCMA NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	depends on BCMA_NFLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	depends on BCMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	  BCMA bus can have various flash memories attached, they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	  registered by bcma as platform devices. This enables driver for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	  NAND flash memories. For now only BCM4706 is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) config MTD_NAND_OXNAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	tristate "Oxford Semiconductor NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	depends on ARCH_OXNAS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	  This enables the NAND flash controller on Oxford Semiconductor SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) config MTD_NAND_MPC5121_NFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tristate "MPC5121 NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	depends on PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	  This enables the driver for the NAND flash controller on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	  MPC5121 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) config MTD_NAND_GPMI_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	tristate "Freescale GPMI NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	depends on MXS_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	  Enables NAND Flash support for IMX23, IMX28 or IMX6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	  The GPMI controller is very powerful, with the help of BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	  module, it can do the hardware ECC. The GPMI supports several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	  NAND flashs at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) config MTD_NAND_FSL_ELBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	tristate "Freescale eLBC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	depends on FSL_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	select FSL_LBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	  Various Freescale chips, including the 8313, include a NAND Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	  Controller Module with built-in hardware ECC capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	  Enabling this option will enable you to use this to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	  external NAND devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) config MTD_NAND_FSL_IFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	tristate "Freescale IFC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	select FSL_IFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	select MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	  Various Freescale chips e.g P1010, include a NAND Flash machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	  with built-in hardware ECC capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	  Enabling this option will enable you to use this to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	  external NAND devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) config MTD_NAND_FSL_UPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	tristate "Freescale UPM NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	depends on PPC_83xx || PPC_85xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	select FSL_LBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	  Enables support for NAND Flash chips wired onto Freescale PowerPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	  processor localbus with User-Programmable Machine support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) config MTD_NAND_VF610_NFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	tristate "Freescale VF610/MPC5125 NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	depends on (SOC_VF610 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	  Enables support for NAND Flash Controller on some Freescale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	  processors like the VF610, MPC5125, MCF54418 or Kinetis K70.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	  The driver supports a maximum 2k page size. With 2k pages and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	  64 bytes or more of OOB, hardware ECC with up to 32-bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	  correction is supported. Hardware ECC is only enabled through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	  device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) config MTD_NAND_MXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	tristate "Freescale MXC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	depends on ARCH_MXC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	  This enables the driver for the NAND flash controller on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	  MXC processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) config MTD_NAND_SH_FLCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	tristate "Renesas SuperH FLCTL NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	depends on SUPERH || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	  Several Renesas SuperH CPU has FLCTL. This option enables support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	  for NAND Flash using FLCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) config MTD_NAND_DAVINCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	tristate "DaVinci/Keystone NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	  Enable the driver for NAND flash chips on Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	  DaVinci/Keystone processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) config MTD_NAND_TXX9NDFMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	tristate "TXx9 NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	depends on SOC_TX4938 || SOC_TX4939 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	  This enables the NAND flash controller on the TXx9 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) config MTD_NAND_SOCRATES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	tristate "Socrates NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	depends on SOCRATES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	  Enables support for NAND Flash chips wired onto Socrates board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) source "drivers/mtd/nand/raw/ingenic/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) config MTD_NAND_FSMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	tristate "ST Micros FSMC NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	depends on OF && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		   COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	  Enables support for NAND Flash chips on the ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	  Flexible Static Memory Controller (FSMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) config MTD_NAND_XWAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	bool "Lantiq XWAY NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	depends on LANTIQ && SOC_TYPE_XWAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	  to the External Bus Unit (EBU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) config MTD_NAND_SUNXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	tristate "Allwinner NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	depends on ARCH_SUNXI || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	  Enables support for NAND Flash chips on Allwinner SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) config MTD_NAND_HISI504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	tristate "Hisilicon Hip04 NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	depends on ARCH_HISI || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	  Enables support for NAND controller on Hisilicon SoC Hip04.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) config MTD_NAND_QCOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	tristate "QCOM NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	depends on ARCH_QCOM || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	  Enables support for NAND flash chips on SoCs containing the EBI2 NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	  controller. This controller is found on IPQ806x SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) config MTD_NAND_MTK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	tristate "MTK NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	depends on ARCH_MEDIATEK || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	  Enables support for NAND controller on MTK SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) config MTD_NAND_MXIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	tristate "Macronix raw NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	depends on HAS_IOMEM || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	  This selects the Macronix raw NAND controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) config MTD_NAND_TEGRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	tristate "NVIDIA Tegra NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	depends on ARCH_TEGRA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	  Enables support for NAND flash controller on NVIDIA Tegra SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	  The driver has been developed and tested on a Tegra 2 SoC. DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	  support, raw read/write page as well as HW ECC read/write page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	  is supported. Extra OOB bytes when using HW ECC are currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	  not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) config MTD_NAND_STM32_FMC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	tristate "Support for NAND controller on STM32MP SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	depends on MACH_STM32MP157 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	  Enables support for NAND Flash chips on SoCs containing the FMC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	  NAND controller. This controller is found on STM32MP SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	  The controller supports a maximum 8k page size and supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	  a maximum 8-bit correction error per sector of 512 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) config MTD_NAND_MESON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	tristate "Support for NAND controller on Amlogic's Meson SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	depends on ARCH_MESON || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	  Enables support for NAND controller on Amlogic's Meson SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	  This controller is found on Meson SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) config MTD_NAND_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	tristate "GPIO assisted NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	depends on GPIOLIB || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	  This enables a NAND flash driver where control signals are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	  connected to GPIO pins, and commands and data are communicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	  via a memory mapped interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) config MTD_NAND_PLATFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	tristate "Generic NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	  This implements a generic NAND driver for on-SOC platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	  devices. You will need to provide platform-specific functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	  via platform_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) config MTD_NAND_CADENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	tristate "Support Cadence NAND (HPNFC) controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	depends on (OF || COMPILE_TEST) && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	  Enable the driver for NAND flash on platforms using a Cadence NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	  controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) config MTD_NAND_ARASAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	tristate "Support for Arasan NAND flash controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	depends on HAS_IOMEM && HAS_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	select BCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	  Enables the driver for the Arasan NAND flash controller on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	  Zynq Ultrascale+ MPSoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) config MTD_NAND_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	tristate "Rockchip NAND controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	depends on ARCH_ROCKCHIP && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	  Enables support for NAND controller on Rockchip SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	  There are four different versions of NAND FLASH Controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	  including:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	    NFC v600: RK2928, RK3066, RK3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	    NFC v622: RK3036, RK3128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	    NFC v800: RK3308, RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	    NFC v900: PX30, RK3326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) comment "Misc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) config MTD_SM_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) config MTD_NAND_NANDSIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	tristate "Support for NAND Flash Simulator"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	  The simulator may simulate various NAND flash chips for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	  MTD nand layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) config MTD_NAND_RICOH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	tristate "Ricoh xD card reader"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	select MTD_SM_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	  Enable support for Ricoh R5C852 xD card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	  You also need to enable ether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	  NAND SSFDC (SmartMedia) read only translation layer' or new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	  expermental, readwrite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	  'SmartMedia/xD new translation layer'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) config MTD_NAND_DISKONCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	select REED_SOLOMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	select REED_SOLOMON_DEC16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	  This is a reimplementation of M-Systems DiskOnChip 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	  Millennium and Millennium Plus as a standard NAND device driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	  as opposed to the earlier self-contained MTD device drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	  This should enable, among other things, proper JFFS2 operation on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	  these devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) config MTD_NAND_DISKONCHIP_PROBE_ADVANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	bool "Advanced detection options for DiskOnChip"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	depends on MTD_NAND_DISKONCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	  This option allows you to specify nonstandard address at which to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	  probe for a DiskOnChip, or to change the detection options.  You
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	  are unlikely to need any of this unless you are using LinuxBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	  Say 'N'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) config MTD_NAND_DISKONCHIP_PROBE_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	depends on MTD_NAND_DISKONCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	default "0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	  By default, the probe for DiskOnChip devices will look for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	  DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	  This option allows you to specify a single address at which to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	  for the device, which is useful if you have other devices in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	  range which get upset when they are probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	  (Note that on PowerPC, the normal probe will only check at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	  0xE4000000.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	  Normally, you should leave this set to zero, to allow the probe at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	  the normal addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) config MTD_NAND_DISKONCHIP_PROBE_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	bool "Probe high addresses"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	  By default, the probe for DiskOnChip devices will look for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	  DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	  This option changes to make it probe between 0xFFFC8000 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	  0xFFFEE000.  Unless you are using LinuxBIOS, this is unlikely to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	  useful to you.  Say 'N'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) config MTD_NAND_DISKONCHIP_BBTWRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	depends on MTD_NAND_DISKONCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	  On DiskOnChip devices shipped with the INFTL filesystem (Millennium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	  and 2000 TSOP/Alon), Linux reserves some space at the end of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	  device for the Bad Block Table (BBT).  If you have existing INFTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	  data on your device (created by non-Linux tools such as M-Systems'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	  DOS drivers), your data might overlap the area Linux wants to use for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	  the BBT.  If this is a concern for you, leave this option disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	  Linux will not write BBT data into this area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	  The downside of leaving this option disabled is that if bad blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	  are detected by Linux, they will not be recorded in the BBT, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	  could cause future problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	  Once you enable this option, new filesystems (INFTL or others, created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	  in Linux or other operating systems) will not use the reserved area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	  The only reason not to enable this option is to prevent damage to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	  preexisting filesystems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	  Even if you leave this disabled, you can enable BBT writes at module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	  load time (assuming you build diskonchip as a module) with the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	  parameter "inftl_bbt_write=1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) endif # MTD_RAW_NAND