Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright (C) 2008-2010 Samsung Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Kyungmin Park <kyungmin.park@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __SAMSUNG_ONENAND_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __SAMSUNG_ONENAND_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * OneNAND Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MEM_CFG_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BURST_LEN_OFFSET	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MEM_RESET_OFFSET	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define INT_ERR_STAT_OFFSET	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INT_ERR_MASK_OFFSET	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INT_ERR_ACK_OFFSET	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ECC_ERR_STAT_OFFSET	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MANUFACT_ID_OFFSET	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEVICE_ID_OFFSET	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DATA_BUF_SIZE_OFFSET	0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BOOT_BUF_SIZE_OFFSET	0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BUF_AMOUNT_OFFSET	0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TECH_OFFSET		0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FBA_WIDTH_OFFSET	0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FPA_WIDTH_OFFSET	0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSA_WIDTH_OFFSET	0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TRANS_SPARE_OFFSET	0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DBS_DFS_WIDTH_OFFSET	0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INT_PIN_ENABLE_OFFSET	0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACC_CLOCK_OFFSET	0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FLASH_VER_ID_OFFSET	0x01F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FLASH_AUX_CNTRL_OFFSET	0x0300		/* s3c64xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ONENAND_MEM_RESET_HOT	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ONENAND_MEM_RESET_COLD	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ONENAND_MEM_RESET_WARM	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CACHE_OP_ERR		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RST_CMP			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RDY_ACT			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define INT_ACT			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UNSUP_CMD		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LOCKED_BLK		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BLK_RW_CMP		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ERS_CMP			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PGM_CMP			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LOAD_CMP		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ERS_FAIL		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PGM_FAIL		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INT_TO			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LD_FAIL_ECC_ERR		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TSRF			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif