Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) menuconfig MTD_ONENAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	tristate "OneNAND Device Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	  This enables support for accessing all type of OneNAND flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	  devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) if MTD_ONENAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) config MTD_ONENAND_VERIFY_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	bool "Verify OneNAND page writes"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	  This adds an extra check when data is written to the flash. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	  OneNAND flash device internally checks only bits transitioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	  from 1 to 0. There is a rare possibility that even though the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	  device thinks the write was successful, a bit could have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	  flipped accidentally due to device wear or something else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) config MTD_ONENAND_GENERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	tristate "OneNAND Flash device via platform device driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	  Support for OneNAND flash via platform device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) config MTD_ONENAND_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	tristate "OneNAND on OMAP2/OMAP3 support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	depends on ARCH_OMAP2 || ARCH_OMAP3 || (COMPILE_TEST && ARM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	depends on OF || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	  via the GPMC memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	  Enable dmaengine and gpiolib for better performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) config MTD_ONENAND_SAMSUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	tristate "OneNAND on Samsung SOC controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	  Support for a OneNAND flash device connected to an Samsung SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	  S3C64XX uses command mapping method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	  S5PC110/S5PC210 use generic OneNAND method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) config MTD_ONENAND_OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bool "OneNAND OTP Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	  One Block of the NAND Flash Array memory is reserved as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	  a One-Time Programmable Block memory area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	  Also, 1st Block of NAND Flash Array can be used as OTP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	  The OTP block can be read, programmed and locked using the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	  operations as any other NAND Flash Array memory block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	  OTP block cannot be erased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	  OTP block is fully-guaranteed to be a valid block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) config MTD_ONENAND_2X_PROGRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	bool "OneNAND 2X program support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	  The 2X Program is an extension of Program Operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	  Since the device is equipped with two DataRAMs, and two-plane NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	  Flash memory array, these two component enables simultaneous program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	  of 4KiB. Plane1 has only even blocks such as block0, block2, block4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	  while Plane2 has only odd blocks such as block1, block3, block5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	  So MTD regards it as 4KiB page size and 256KiB block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	  Now the following chips support it. (KFXXX16Q2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	    Demux: KFG2G16Q2M, KFH4G16Q2M, KFW8G16Q2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	    Mux:   KFM2G16Q2M, KFN4G16Q2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	  And more recent chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) endif # MTD_ONENAND