^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic Error-Correcting Code (ECC) engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Macronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Miquèl RAYNAL <miquel.raynal@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file describes the abstraction of any NAND ECC engine. It has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * designed to fit most cases, including parallel NANDs and SPI-NANDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * There are three main situations where instantiating this ECC engine makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * sense:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - external: The ECC engine is outside the NAND pipeline, typically this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * is a software ECC engine, or an hardware engine that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * outside the NAND controller pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * controller's side. This is the case of most of the raw NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * controllers. In the pipeline case, the ECC bytes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * generated/data corrected on the fly when a page is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * written/read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Some NAND chips can correct themselves the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Besides the initial setup and final cleanups, the interfaces are rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * simple:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the I/O request type. In case of software correction or external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * engine, this step may involve to derive the ECC bytes and place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * them in the OOB area before a write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - finish: Finish an I/O request. Correct the data in case of a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * request and report the number of corrected bits/uncorrectable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * errors. Most likely empty for write operations, unless you have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * hardware specific stuff to do, like shutting down the engine to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * save power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The I/O request should be enclosed in a prepare()/finish() pair of calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * and will behave differently depending on the requested I/O type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - raw: Correction disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - ecc: Correction enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The request direction is impacting the logic as well:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - read: Load data from the NAND chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * - write: Store data in the NAND chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Mixing all this combinations together gives the following behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Those are just examples, drivers are free to add custom steps in their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * prepare/finish hook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * [external ECC engine]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * - external + prepare + raw + read: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * - external + finish + raw + read: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * - external + prepare + raw + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * - external + finish + raw + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * - external + prepare + ecc + read: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * - external + finish + ecc + read: calculate expected ECC bytes, extract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * ECC bytes from OOB buffer, correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * and report any bitflip/error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * - external + prepare + ecc + write: calculate ECC bytes and store them at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * the right place in the OOB buffer based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * on the OOB layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - external + finish + ecc + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * [pipelined ECC engine]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - pipelined + prepare + raw + read: disable the controller's ECC engine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - pipelined + finish + raw + read: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - pipelined + prepare + raw + write: disable the controller's ECC engine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * - pipelined + finish + raw + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * - pipelined + prepare + ecc + read: enable the controller's ECC engine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * deactivated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * - pipelined + finish + ecc + read: check the status, report any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * error/bitflip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * - pipelined + prepare + ecc + write: enable the controller's ECC engine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * deactivated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * - pipelined + finish + ecc + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * [ondie ECC engine]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * - ondie + prepare + raw + read: send commands to disable the on-chip ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * engine if activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * - ondie + finish + raw + read: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * - ondie + prepare + raw + write: send commands to disable the on-chip ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * engine if activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * - ondie + finish + raw + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * - ondie + prepare + ecc + read: send commands to enable the on-chip ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * engine if deactivated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * - ondie + finish + ecc + read: send commands to check the status, report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * any error/bitflip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * - ondie + prepare + ecc + write: send commands to enable the on-chip ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * engine if deactivated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - ondie + finish + ecc + write: do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/mtd/nand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * nand_ecc_init_ctx - Init the ECC engine context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @nand: the NAND device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * On success, the caller is responsible of calling @nand_ecc_cleanup_ctx().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int nand_ecc_init_ctx(struct nand_device *nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!nand->ecc.engine->ops->init_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return nand->ecc.engine->ops->init_ctx(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXPORT_SYMBOL(nand_ecc_init_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * nand_ecc_cleanup_ctx - Cleanup the ECC engine context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @nand: the NAND device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void nand_ecc_cleanup_ctx(struct nand_device *nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (nand->ecc.engine->ops->cleanup_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) nand->ecc.engine->ops->cleanup_ctx(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXPORT_SYMBOL(nand_ecc_cleanup_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * nand_ecc_prepare_io_req - Prepare an I/O request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @nand: the NAND device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @req: the I/O request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int nand_ecc_prepare_io_req(struct nand_device *nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct nand_page_io_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!nand->ecc.engine->ops->prepare_io_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return nand->ecc.engine->ops->prepare_io_req(nand, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EXPORT_SYMBOL(nand_ecc_prepare_io_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * nand_ecc_finish_io_req - Finish an I/O request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @nand: the NAND device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @req: the I/O request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int nand_ecc_finish_io_req(struct nand_device *nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct nand_page_io_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!nand->ecc.engine->ops->finish_io_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return nand->ecc.engine->ops->finish_io_req(nand, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL(nand_ecc_finish_io_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Define default OOB placement schemes for large and small page devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct nand_device *nand = mtd_to_nanddev(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int total_ecc_bytes = nand->ecc.ctx.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (section > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!section) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) oobregion->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (mtd->oobsize == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) oobregion->length = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) oobregion->length = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (mtd->oobsize == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) oobregion->offset = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) oobregion->length = total_ecc_bytes - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (section > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (mtd->oobsize == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) oobregion->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) oobregion->offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) oobregion->length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) oobregion->offset = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) oobregion->offset = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ecc = nand_ooblayout_ecc_sp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .free = nand_ooblayout_free_sp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct mtd_ooblayout_ops *nand_get_small_page_ooblayout(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return &nand_ooblayout_sp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL_GPL(nand_get_small_page_ooblayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct nand_device *nand = mtd_to_nanddev(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int total_ecc_bytes = nand->ecc.ctx.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (section || !total_ecc_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) oobregion->length = total_ecc_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) oobregion->offset = mtd->oobsize - oobregion->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct nand_device *nand = mtd_to_nanddev(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int total_ecc_bytes = nand->ecc.ctx.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) oobregion->length = mtd->oobsize - total_ecc_bytes - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) oobregion->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ecc = nand_ooblayout_ecc_lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .free = nand_ooblayout_free_lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return &nand_ooblayout_lp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL_GPL(nand_get_large_page_ooblayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * are placed at a fixed offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct nand_device *nand = mtd_to_nanddev(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int total_ecc_bytes = nand->ecc.ctx.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (mtd->oobsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) oobregion->offset = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) oobregion->offset = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) oobregion->length = total_ecc_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (oobregion->offset + oobregion->length > mtd->oobsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mtd_oob_region *oobregion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct nand_device *nand = mtd_to_nanddev(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int total_ecc_bytes = nand->ecc.ctx.total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ecc_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (section < 0 || section > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) switch (mtd->oobsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ecc_offset = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ecc_offset = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (section == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) oobregion->offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) oobregion->length = ecc_offset - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) oobregion->offset = ecc_offset + total_ecc_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) oobregion->length = mtd->oobsize - oobregion->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .ecc = nand_ooblayout_ecc_lp_hamming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .free = nand_ooblayout_free_lp_hamming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct mtd_ooblayout_ops *nand_get_large_page_hamming_ooblayout(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return &nand_ooblayout_lp_hamming_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) EXPORT_SYMBOL_GPL(nand_get_large_page_hamming_ooblayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static enum nand_ecc_engine_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) of_get_nand_ecc_engine_type(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device_node *eng_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (of_property_read_bool(np, "nand-no-ecc-engine"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return NAND_ECC_ENGINE_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (of_property_read_bool(np, "nand-use-soft-ecc-engine"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return NAND_ECC_ENGINE_TYPE_SOFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) eng_np = of_parse_phandle(np, "nand-ecc-engine", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) of_node_put(eng_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (eng_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (eng_np == np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return NAND_ECC_ENGINE_TYPE_ON_DIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return NAND_ECC_ENGINE_TYPE_ON_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return NAND_ECC_ENGINE_TYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const char * const nand_ecc_placement[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [NAND_ECC_PLACEMENT_OOB] = "oob",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum nand_ecc_placement placement;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const char *pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) err = of_property_read_string(np, "nand-ecc-placement", &pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (placement = NAND_ECC_PLACEMENT_OOB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) placement < ARRAY_SIZE(nand_ecc_placement); placement++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!strcasecmp(pm, nand_ecc_placement[placement]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return placement;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return NAND_ECC_PLACEMENT_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const nand_ecc_algos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [NAND_ECC_ALGO_HAMMING] = "hamming",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [NAND_ECC_ALGO_BCH] = "bch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [NAND_ECC_ALGO_RS] = "rs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum nand_ecc_algo ecc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const char *pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) err = of_property_read_string(np, "nand-ecc-algo", &pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (ecc_algo = NAND_ECC_ALGO_HAMMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ecc_algo < ARRAY_SIZE(nand_ecc_algos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ecc_algo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!strcasecmp(pm, nand_ecc_algos[ecc_algo]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ecc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return NAND_ECC_ALGO_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int of_get_nand_ecc_step_size(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret ? ret : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int of_get_nand_ecc_strength(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = of_property_read_u32(np, "nand-ecc-strength", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret ? ret : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void of_get_nand_ecc_user_config(struct nand_device *nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct device_node *dn = nanddev_get_of_node(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int strength, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) nand->ecc.user_conf.engine_type = of_get_nand_ecc_engine_type(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) nand->ecc.user_conf.algo = of_get_nand_ecc_algo(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) nand->ecc.user_conf.placement = of_get_nand_ecc_placement(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) strength = of_get_nand_ecc_strength(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (strength >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) nand->ecc.user_conf.strength = strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) size = of_get_nand_ecc_step_size(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (size >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) nand->ecc.user_conf.step_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (of_property_read_bool(dn, "nand-ecc-maximize"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) nand->ecc.user_conf.flags |= NAND_ECC_MAXIMIZE_STRENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) EXPORT_SYMBOL(of_get_nand_ecc_user_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * nand_ecc_is_strong_enough - Check if the chip configuration meets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * datasheet requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * @nand: Device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * If our configuration corrects A bits per B bytes and the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * required correction level is X bits per Y bytes, then we must ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * both of the following are true:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * (1) A / B >= X / Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * (2) A >= X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Requirement (1) ensures we can correct for the required bitflip density.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Requirement (2) ensures we can correct even when all bitflips are clumped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * in the same sector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bool nand_ecc_is_strong_enough(struct nand_device *nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) const struct nand_ecc_props *reqs = nanddev_get_ecc_requirements(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const struct nand_ecc_props *conf = nanddev_get_ecc_conf(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mtd_info *mtd = nanddev_to_mtd(nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int corr, ds_corr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (conf->step_size == 0 || reqs->step_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Not enough information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * We get the number of corrected bits per page to compare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * the correction density.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) corr = (mtd->writesize * conf->strength) / conf->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ds_corr = (mtd->writesize * reqs->strength) / reqs->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return corr >= ds_corr && conf->strength >= reqs->strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL(nand_ecc_is_strong_enough);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("Generic ECC engine");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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