^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The SC520CDP is an evaluation board for the Elan SC520 processor available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and up to 512 KiB of 8-bit DIL Flash ROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * For details see https://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/concat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** The Embedded Systems BIOS decodes the first FLASH starting at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** 0x8400000. This is a *terrible* place for it because accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** the flash at this location causes the A22 address line to be high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** (that's what 0x8400000 binary's ought to be). But this is the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** order address line on the raw flash devices themselves!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** This causes the top HALF of the flash to be accessed first. Beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** the physical limits of the flash, the flash chip aliases over (to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ** 0x880000 which causes the bottom half to be accessed. This splits the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ** flash into two and inverts it! If you then try to access this from another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ** program that does NOT do this insanity, then you *will* access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** first half of the flash, but not find what you expect there. That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** stuff is in the *second* half! Similarly, the address used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ** BIOS for the second FLASH bank is also quite a bad choice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** If REPROGRAM_PAR is defined below (the default), then this driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** choose more useful addresses for the FLASH banks by reprogramming the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** responsible PARxx registers in the SC520's MMCR region. This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** cause the settings to be incompatible with the BIOS's settings, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ** shouldn't be a problem since you are running Linux, (i.e. the BIOS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ** not much use anyway). However, if you need to be compatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ** the BIOS for some reason, just undefine REPROGRAM_PAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REPROGRAM_PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef REPROGRAM_PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* These are the addresses we want.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WINDOW_ADDR_0 0x08800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WINDOW_ADDR_1 0x09000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WINDOW_ADDR_2 0x09800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* .. and these are the addresses the BIOS gives us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WINDOW_ADDR_0_BIOS 0x08400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WINDOW_ADDR_1_BIOS 0x08c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WINDOW_ADDR_2_BIOS 0x09400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WINDOW_ADDR_0 0x08400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WINDOW_ADDR_1 0x08C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WINDOW_ADDR_2 0x09400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WINDOW_SIZE_0 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WINDOW_SIZE_1 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WINDOW_SIZE_2 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct map_info sc520cdp_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "SC520CDP Flash Bank #0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .size = WINDOW_SIZE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .bankwidth = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .phys = WINDOW_ADDR_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "SC520CDP Flash Bank #1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .size = WINDOW_SIZE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .bankwidth = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .phys = WINDOW_ADDR_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "SC520CDP DIL Flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .size = WINDOW_SIZE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .bankwidth = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .phys = WINDOW_ADDR_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct mtd_info *mymtd[NUM_FLASH_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct mtd_info *merged_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef REPROGRAM_PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ** The SC520 MMCR (memory mapped control register) region resides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ** are at offset 0x88 in the MMCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC520_MMCR_BASE 0xFFFEF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC520_MMCR_EXTENT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC520_PAR(x) ((0x88/sizeof(unsigned long)) + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NUM_SC520_PAR 16 /* total number of PAR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ** The highest three bits in a PAR register determine what target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ** device is controlled by this PAR. Here, only ROMCS? and BOOTCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ** devices are of interest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC520_PAR_BOOTCS (0x4<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SC520_PAR_ROMCS0 (0x5<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SC520_PAR_ROMCS1 (0x6<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SC520_PAR_TRGDEV (0x7<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ** Bits 28 thru 26 determine some attributes for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ** region controlled by the PAR. (We only use non-cacheable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SC520_PAR_WRPROT (1<<26) /* write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SC520_PAR_NOCACHE (1<<27) /* non-cacheable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SC520_PAR_NOEXEC (1<<28) /* code execution denied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ** Bit 25 determines the granularity: 4K or 64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SC520_PAR_PG_SIZ4 (0<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SC520_PAR_PG_SIZ64 (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ** Build a value to be written into a PAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ** We only need ROM entries, 64K page size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SC520_PAR_ENTRY(trgdev, address, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (address) >> 16 | (((size) >> 16) - 1) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct sc520_par_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long trgdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long new_par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long default_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { /* Flash Bank #0: selected by ROMCS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SC520_PAR_ROMCS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) WINDOW_ADDR_0_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { /* Flash Bank #1: selected by ROMCS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SC520_PAR_ROMCS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) WINDOW_ADDR_1_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { /* DIL (BIOS) Flash: selected by BOOTCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SC520_PAR_BOOTCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) WINDOW_ADDR_2_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void sc520cdp_setup_par(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long __iomem *mmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long mmcr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* map in SC520's MMCR area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mmcr = ioremap(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if(!mmcr) { /* ioremap failed: skip the PAR reprogramming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* force physical address fields to BIOS defaults: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for(i = 0; i < NUM_FLASH_BANKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sc520cdp_map[i].phys = par_table[i].default_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ** Find the PARxx registers that are responsible for activating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ** new value from the table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for(i = 0; i < NUM_FLASH_BANKS; i++) { /* for each par_table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for(j = 0; j < NUM_SC520_PAR; j++) { /* for each PAR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mmcr_val = readl(&mmcr[SC520_PAR(j)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* if target device field matches, reprogram the PAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if(j == NUM_SC520_PAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { /* no matching PAR found: try default BIOS address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sc520cdp_map[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) printk(KERN_NOTICE "Trying default address 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) par_table[i].default_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sc520cdp_map[i].phys = par_table[i].default_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iounmap(mmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init init_sc520cdp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int i, j, devices_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef REPROGRAM_PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* reprogram PAR registers so flash appears at the desired addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sc520cdp_setup_par();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 0; i < NUM_FLASH_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (unsigned long long)sc520cdp_map[i].size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (unsigned long long)sc520cdp_map[i].phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sc520cdp_map[i].virt = ioremap(sc520cdp_map[i].phys, sc520cdp_map[i].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!sc520cdp_map[i].virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) printk("Failed to ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (j = 0; j < i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (mymtd[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) map_destroy(mymtd[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) iounmap(sc520cdp_map[j].virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) simple_map_init(&sc520cdp_map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if(!mymtd[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if(!mymtd[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (mymtd[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mymtd[i]->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ++devices_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) iounmap(sc520cdp_map[i].virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if(devices_found >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Combine the two flash banks into a single MTD device & register it: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if(merged_mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mtd_device_register(merged_mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if(devices_found == 3) /* register the third (DIL-Flash) device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mtd_device_register(mymtd[2], NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return(devices_found ? 0 : -ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __exit cleanup_sc520cdp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (merged_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mtd_device_unregister(merged_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mtd_concat_destroy(merged_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (mymtd[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mtd_device_unregister(mymtd[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) for (i = 0; i < NUM_FLASH_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (mymtd[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) map_destroy(mymtd[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (sc520cdp_map[i].virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) iounmap(sc520cdp_map[i].virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sc520cdp_map[i].virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) module_init(init_sc520cdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_exit(cleanup_sc520cdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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