^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel IXP4xx OF physmap add-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on the ixp4xx.c map driver, originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Deepak Saxena <dsaxena@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2002 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2003-2004 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/xip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "physmap-ixp4xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Read/write a 16 bit word from flash address 'addr'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * When the cpu is in little-endian mode it swizzles the address lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ('address coherency') so we need to undo the swizzling to ensure commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * and the like end up on the correct flash address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * To further complicate matters, due to the way the expansion bus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * handles 32 bit reads, the byte stream ABCD is stored on the flash as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * D15 D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * +---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | A | B | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * +---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * | C | D | 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * +---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * This means that on LE systems each 16 bit word must be swapped. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * this requires CONFIG_MTD_CFI_BE_BYTE_SWAP to be enabled to 'unswap' the CFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * data and other flash commands which are always in D7-D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline u16 flash_read16(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return be16_to_cpu(__raw_readw((void __iomem *)((unsigned long)addr ^ 0x2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void flash_write16(u16 d, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __raw_writew(cpu_to_be16(d), (void __iomem *)((unsigned long)addr ^ 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BYTE0(h) ((h) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BYTE1(h) (((h) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline u16 flash_read16(const void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return __raw_readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void flash_write16(u16 d, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_writew(d, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BYTE0(h) (((h) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BYTE1(h) ((h) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static map_word ixp4xx_read16(struct map_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val.x[0] = flash_read16(map->virt + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * The IXP4xx expansion bus only allows 16-bit wide acceses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * when attached to a 16-bit wide device (such as the 28F128J3A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * so we can't just memcpy_fromio().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void ixp4xx_copy_from(struct map_info *map, void *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 *dest = (u8 *) to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *src = map->virt + from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (from & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *dest++ = BYTE1(flash_read16(src-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) --len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 data = flash_read16(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *dest++ = BYTE0(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *dest++ = BYTE1(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) src += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *dest++ = BYTE0(flash_read16(src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void ixp4xx_write16(struct map_info *map, map_word d, unsigned long adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) flash_write16(d.x[0], map->virt + adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int of_flash_probe_ixp4xx(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct map_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Multiplatform guard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!of_device_is_compatible(np, "intel,ixp4xx-flash"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) map->read = ixp4xx_read16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) map->write = ixp4xx_write16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) map->copy_from = ixp4xx_copy_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) map->copy_to = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_info(dev, "initialized Intel IXP4xx-specific physmap control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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