^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mtd/maps/pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Russell King, All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Generic PCI memory map driver. We support the following boards:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Intel IQ80310 ATU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Intel EBSA285 (blank rom programming mode). Tested working 27/09/2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct map_pci_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mtd_pci_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int (*init)(struct pci_dev *dev, struct map_pci_info *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void (*exit)(struct pci_dev *dev, struct map_pci_info *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long (*translate)(struct map_pci_info *map, unsigned long ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const char *map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct map_pci_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct map_info map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void (*exit)(struct pci_dev *dev, struct map_pci_info *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long (*translate)(struct map_pci_info *map, unsigned long ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static map_word mtd_pci_read8(struct map_info *_map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) val.x[0]= readb(map->base + map->translate(map, ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static map_word mtd_pci_read32(struct map_info *_map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val.x[0] = readl(map->base + map->translate(map, ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void mtd_pci_copyfrom(struct map_info *_map, void *to, unsigned long from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) memcpy_fromio(to, map->base + map->translate(map, from), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void mtd_pci_write8(struct map_info *_map, map_word val, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writeb(val.x[0], map->base + map->translate(map, ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void mtd_pci_write32(struct map_info *_map, map_word val, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(val.x[0], map->base + map->translate(map, ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void mtd_pci_copyto(struct map_info *_map, unsigned long to, const void *from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct map_pci_info *map = (struct map_pci_info *)_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) memcpy_toio(map->base + map->translate(map, to), from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct map_info mtd_pci_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .phys = NO_XIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .copy_from = mtd_pci_copyfrom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .copy_to = mtd_pci_copyto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Intel IOP80310 Flash driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) intel_iq80310_init(struct pci_dev *dev, struct map_pci_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 win_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) map->map.bankwidth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) map->map.read = mtd_pci_read8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) map->map.write = mtd_pci_write8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) map->map.size = 0x00800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) map->base = ioremap(pci_resource_start(dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_resource_len(dev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!map->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * We want to base the memory window at Xscale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * bus address 0, not 0x1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_read_config_dword(dev, 0x44, &win_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pci_write_config_dword(dev, 0x44, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) map->map.map_priv_2 = win_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) intel_iq80310_exit(struct pci_dev *dev, struct map_pci_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (map->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) iounmap(map->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pci_write_config_dword(dev, 0x44, map->map.map_priv_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) intel_iq80310_translate(struct map_pci_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long page_addr = ofs & 0x00400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * This mundges the flash location so we avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * the first 80 bytes (they appear to read nonsense).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (page_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(0x00000008, map->base + 0x1558);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0x00000000, map->base + 0x1550);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(0x00000007, map->base + 0x1558);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(0x00800000, map->base + 0x1550);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ofs += 0x00800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct mtd_pci_info intel_iq80310_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .init = intel_iq80310_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .exit = intel_iq80310_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .translate = intel_iq80310_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Intel DC21285 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) intel_dc21285_init(struct pci_dev *dev, struct map_pci_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long base, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) base = pci_resource_start(dev, PCI_ROM_RESOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) len = pci_resource_len(dev, PCI_ROM_RESOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!len || !base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * No ROM resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) base = pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) len = pci_resource_len(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * We need to re-allocate PCI BAR2 address range to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * PCI ROM BAR, and disable PCI BAR2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Hmm, if an address was allocated to the ROM resource, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * not enabled, should we be allocating a new resource for it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * or simply enabling it?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pci_enable_rom(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk("%s: enabling expansion ROM\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!len || !base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) map->map.bankwidth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) map->map.read = mtd_pci_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) map->map.write = mtd_pci_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) map->map.size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) map->base = ioremap(base, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!map->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) intel_dc21285_exit(struct pci_dev *dev, struct map_pci_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (map->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) iounmap(map->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * We need to undo the PCI BAR2/PCI ROM BAR address alteration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_disable_rom(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) intel_dc21285_translate(struct map_pci_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ofs & 0x00ffffc0 ? ofs : (ofs ^ (1 << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct mtd_pci_info intel_dc21285_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .init = intel_dc21285_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .exit = intel_dc21285_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .translate = intel_dc21285_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .map_name = "jedec_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * PCI device ID table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct pci_device_id mtd_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .vendor = PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .device = 0x530d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .class = PCI_CLASS_MEMORY_OTHER << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .class_mask = 0xffff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .driver_data = (unsigned long)&intel_iq80310_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .vendor = PCI_VENDOR_ID_DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .device = PCI_DEVICE_ID_DEC_21285,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .subvendor = 0, /* DC21285 defaults to 0 on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .subdevice = 0, /* DC21285 defaults to 0 on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .driver_data = (unsigned long)&intel_dc21285_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Generic code follows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int mtd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mtd_pci_info *info = (struct mtd_pci_info *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct map_pci_info *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mtd_info *mtd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = pci_request_regions(dev, "pci mtd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) map = kmalloc(sizeof(*map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) map->map = mtd_pci_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) map->map.name = pci_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) map->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) map->exit = info->exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) map->translate = info->translate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err = info->init(dev, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mtd = do_map_probe(info->map_name, &map->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mtd_device_register(mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pci_set_drvdata(dev, mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) map->exit(dev, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void mtd_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mtd_info *mtd = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct map_pci_info *map = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mtd_device_unregister(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) map_destroy(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) map->exit(dev, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct pci_driver mtd_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "MTD PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .probe = mtd_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .remove = mtd_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .id_table = mtd_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) module_pci_driver(mtd_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DESCRIPTION("Generic PCI map driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DEVICE_TABLE(pci, mtd_pci_ids);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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