^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mtd/cfi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/root_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define INTEL_BUSWIDTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AMD_WINDOW_MAXSIZE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AMD_BUSWIDTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * PAR masks and shifts, assuming 64K pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC520_PAR_ADDR_MASK 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC520_PAR_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC520_PAR_TO_ADDR(par) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (((par)&SC520_PAR_ADDR_MASK) << SC520_PAR_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC520_PAR_SIZE_MASK 0x01ffc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SC520_PAR_SIZE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC520_PAR_TO_SIZE(par) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ((((par)&SC520_PAR_SIZE_MASK) << SC520_PAR_SIZE_SHIFT) + (64*1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC520_PAR(cs, addr, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((cs) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (((addr) >> SC520_PAR_ADDR_SHIFT) & SC520_PAR_ADDR_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC520_PAR_BOOTCS 0x8a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC520_PAR_ROMCS1 0xaa000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC520_PAR_ROMCS2 0xca000000 /* Cache disabled, 64K page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void *nettel_mmcrp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct mtd_info *intel_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct mtd_info *amd_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct map_info nettel_intel_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "SnapGear Intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .bankwidth = INTEL_BUSWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct mtd_partition nettel_intel_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "SnapGear kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .size = 0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "SnapGear filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .offset = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .name = "SnapGear config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .offset = 0x000e0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .size = 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "SnapGear Intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .offset = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "SnapGear BIOS Config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .offset = 0x007e0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .size = 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "SnapGear BIOS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .offset = 0x007e0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .size = 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct map_info nettel_amd_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "SnapGear AMD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .size = AMD_WINDOW_MAXSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .bankwidth = AMD_BUSWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct mtd_partition nettel_amd_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "SnapGear BIOS config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .offset = 0x000e0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .size = 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "SnapGear BIOS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .offset = 0x000f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .size = 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "SnapGear AMD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .offset = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "SnapGear high BIOS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .offset = 0x001f0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .size = 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NUM_AMD_PARTITIONS ARRAY_SIZE(nettel_amd_partitions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Set the Intel flash back to read mode since some old boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * loaders don't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cfi_private *cfi = nettel_intel_map.fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Make sure all FLASH chips are put back into read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) for (b = 0; (b < nettel_intel_partitions[3].size); b += 0x100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cfi->device_type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return(NOTIFY_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct notifier_block nettel_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) nettel_reboot_notifier, NULL, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int __init nettel_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) volatile unsigned long *amdpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long amdaddr, maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int num_amd_partitions=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) volatile unsigned long *intel0par, *intel1par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long orig_bootcspar, orig_romcs1par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long intel0addr, intel0size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long intel1addr, intel1size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int intelboot, intel0cs, intel1cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int num_intel_partitions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) nettel_mmcrp = (void *) ioremap(0xfffef000, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (nettel_mmcrp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk("SNAPGEAR: failed to disable MMCR cache??\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return(-EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Set CPU clock to be 33.000MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *((unsigned char *) (nettel_mmcrp + 0xc64)) = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) amdpar = (volatile unsigned long *) (nettel_mmcrp + 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) intelboot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) intel0cs = SC520_PAR_ROMCS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) intel0par = (volatile unsigned long *) (nettel_mmcrp + 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) intel1cs = SC520_PAR_ROMCS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) intel1par = (volatile unsigned long *) (nettel_mmcrp + 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Save the CS settings then ensure ROMCS1 and ROMCS2 are off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * otherwise they might clash with where we try to map BOOTCS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) orig_bootcspar = *amdpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) orig_romcs1par = *intel0par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *intel0par = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *intel1par = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * The first thing to do is determine if we have a separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * boot FLASH device. Typically this is a small (1 to 2MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * AMD FLASH part. It seems that device size is about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * only way to tell if this is the case...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) amdaddr = 0x20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) maxsize = AMD_WINDOW_MAXSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *amdpar = SC520_PAR(SC520_PAR_BOOTCS, amdaddr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __asm__ ("wbinvd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) nettel_amd_map.phys = amdaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) nettel_amd_map.virt = ioremap(amdaddr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!nettel_amd_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) printk("SNAPGEAR: failed to ioremap() BOOTCS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iounmap(nettel_mmcrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return(-EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) simple_map_init(&nettel_amd_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((amd_mtd = do_map_probe("jedec_probe", &nettel_amd_map))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) printk(KERN_NOTICE "SNAPGEAR: AMD flash device size = %dK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (int)(amd_mtd->size>>10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) amd_mtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* The high BIOS partition is only present for 2MB units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) num_amd_partitions = NUM_AMD_PARTITIONS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (amd_mtd->size < AMD_WINDOW_MAXSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) num_amd_partitions--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Don't add the partition until after the primary INTEL's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Map the Intel flash into memory after the AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * It has to start on a multiple of maxsize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (maxsize < (32 * 1024 * 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) maxsize = (32 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) intel0addr = amdaddr + maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* INTEL boot FLASH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) intelboot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!orig_romcs1par) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) intel0cs = SC520_PAR_BOOTCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) intel0par = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (nettel_mmcrp + 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) intel1cs = SC520_PAR_ROMCS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) intel1par = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (nettel_mmcrp + 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) intel0addr = SC520_PAR_TO_ADDR(orig_bootcspar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) maxsize = SC520_PAR_TO_SIZE(orig_bootcspar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Kernel base is on ROMCS1, not BOOTCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) intel0cs = SC520_PAR_ROMCS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) intel0par = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (nettel_mmcrp + 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) intel1cs = SC520_PAR_BOOTCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) intel1par = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (nettel_mmcrp + 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) intel0addr = SC520_PAR_TO_ADDR(orig_romcs1par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) maxsize = SC520_PAR_TO_SIZE(orig_romcs1par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Destroy useless AMD MTD mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) amd_mtd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iounmap(nettel_amd_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) nettel_amd_map.virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Only AMD flash supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * We have determined the INTEL FLASH configuration, so lets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * go ahead and probe for them now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Set PAR to the maximum size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (maxsize < (32 * 1024 * 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) maxsize = (32 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *intel0par = SC520_PAR(intel0cs, intel0addr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Turn other PAR off so the first probe doesn't find it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *intel1par = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Probe for the size of the first Intel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) nettel_intel_map.size = maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) nettel_intel_map.phys = intel0addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) nettel_intel_map.virt = ioremap(intel0addr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!nettel_intel_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) printk("SNAPGEAR: failed to ioremap() ROMCS1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) simple_map_init(&nettel_intel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!intel_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto out_unmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Set PAR to the detected size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) intel0size = intel_mtd->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *intel0par = SC520_PAR(intel0cs, intel0addr, intel0size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Map second Intel FLASH right after first. Set its size to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * same maxsize used for the first Intel FLASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) intel1addr = intel0addr + intel0size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *intel1par = SC520_PAR(intel1cs, intel1addr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __asm__ ("wbinvd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) maxsize += intel0size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Delete the old map and probe again to do both chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) map_destroy(intel_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) intel_mtd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iounmap(nettel_intel_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) nettel_intel_map.size = maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) nettel_intel_map.virt = ioremap(intel0addr, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!nettel_intel_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) printk("SNAPGEAR: failed to ioremap() ROMCS1/2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) intel_mtd = do_map_probe("cfi_probe", &nettel_intel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (! intel_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto out_unmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) intel1size = intel_mtd->size - intel0size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (intel1size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *intel1par = SC520_PAR(intel1cs, intel1addr, intel1size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __asm__ ("wbinvd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *intel1par = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) printk(KERN_NOTICE "SNAPGEAR: Intel flash device size = %lldKiB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (unsigned long long)(intel_mtd->size >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) intel_mtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) num_intel_partitions = ARRAY_SIZE(nettel_intel_partitions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (intelboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Adjust offset and size of last boot partition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Must allow for BIOS region at end of FLASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nettel_intel_partitions[1].size = (intel0size + intel1size) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (1024*1024 + intel_mtd->erasesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) nettel_intel_partitions[3].size = intel0size + intel1size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) nettel_intel_partitions[4].offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (intel0size + intel1size) - intel_mtd->erasesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) nettel_intel_partitions[4].size = intel_mtd->erasesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) nettel_intel_partitions[5].offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) nettel_intel_partitions[4].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) nettel_intel_partitions[5].size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) nettel_intel_partitions[4].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* No BIOS regions when AMD boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) num_intel_partitions -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) rc = mtd_device_register(intel_mtd, nettel_intel_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) num_intel_partitions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) goto out_map_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (amd_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rc = mtd_device_register(amd_mtd, nettel_amd_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) num_amd_partitions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto out_mtd_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) register_reboot_notifier(&nettel_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) out_mtd_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mtd_device_unregister(intel_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) out_map_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) map_destroy(intel_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) out_unmap1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) iounmap(nettel_intel_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) out_unmap2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) iounmap(nettel_mmcrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iounmap(nettel_amd_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void __exit nettel_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unregister_reboot_notifier(&nettel_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (amd_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mtd_device_unregister(amd_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) map_destroy(amd_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (nettel_mmcrp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) iounmap(nettel_mmcrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) nettel_mmcrp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (nettel_amd_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) iounmap(nettel_amd_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) nettel_amd_map.virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #ifdef CONFIG_MTD_CFI_INTELEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (intel_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mtd_device_unregister(intel_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) map_destroy(intel_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (nettel_intel_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) iounmap(nettel_intel_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) nettel_intel_map.virt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) module_init(nettel_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) module_exit(nettel_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_DESCRIPTION("SnapGear/SecureEdge FLASH support");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /****************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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