^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BIOS Flash chip on Intel 440GX board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Bugs this currently does not work under linuxBIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PIIXE_IOBASE_RESOURCE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WINDOW_ADDR 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WINDOW_SIZE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BUSWIDTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static u32 iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IOBASE iobase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TRIBUF_PORT (IOBASE+0x37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VPP_PORT (IOBASE+0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct mtd_info *mymtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Is this really the vpp port? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static DEFINE_SPINLOCK(l440gx_vpp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int l440gx_vpp_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void l440gx_set_vpp(struct map_info *map, int vpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) spin_lock_irqsave(&l440gx_vpp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (vpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (++l440gx_vpp_refcnt == 1) /* first nested 'on' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) outl(inl(VPP_PORT) | 1, VPP_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (--l440gx_vpp_refcnt == 0) /* last nested 'off' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) outl(inl(VPP_PORT) & ~1, VPP_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) spin_unlock_irqrestore(&l440gx_vpp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct map_info l440gx_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "L440GX BIOS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .size = WINDOW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .bankwidth = BUSWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .phys = WINDOW_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* FIXME verify that this is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * appripriate code for vpp enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .set_vpp = l440gx_set_vpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int __init init_l440gx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pci_dev *dev, *pm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct resource *pm_iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PCI_DEVICE_ID_INTEL_82371AB_0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pm_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!dev || !pm_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) printk(KERN_NOTICE "L440GX flash mapping: failed to find PIIX4 ISA bridge, cannot continue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci_dev_put(pm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) l440gx_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!l440gx_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) printk(KERN_WARNING "Failed to ioremap L440GX flash region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_dev_put(pm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) simple_map_init(&l440gx_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_debug("window_addr = %p\n", l440gx_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Setup the pm iobase resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * This code should move into some kind of generic bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * driver but for the moment I'm content with getting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * allocation correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pm_iobase = &pm_dev->resource[PIIXE_IOBASE_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!(pm_iobase->flags & IORESOURCE_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pm_iobase->name = "pm iobase";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pm_iobase->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pm_iobase->end = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pm_iobase->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Put the current value in the resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_read_config_dword(pm_dev, 0x40, &iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) iobase &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pm_iobase->start += iobase & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pm_iobase->end += iobase & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_dev_put(pm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Allocate the resource region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (pci_assign_resource(pm_dev, PIIXE_IOBASE_RESOURCE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_dev_put(pm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) printk(KERN_WARNING "Could not allocate pm iobase resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) iounmap(l440gx_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Set the iobase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iobase = pm_iobase->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pci_write_config_dword(pm_dev, 0x40, iobase | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Set XBCS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_read_config_word(dev, 0x4e, &word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) word |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_write_config_word(dev, 0x4e, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Supply write voltage to the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) l440gx_set_vpp(&l440gx_map, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Enable the gate on the WE line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mymtd = do_map_probe("jedec_probe", &l440gx_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!mymtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) printk(KERN_NOTICE "JEDEC probe on BIOS chip failed. Using ROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mymtd = do_map_probe("map_rom", &l440gx_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (mymtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mymtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mtd_device_register(mymtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) iounmap(l440gx_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void __exit cleanup_l440gx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mtd_device_unregister(mymtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) map_destroy(mymtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) iounmap(l440gx_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) module_init(init_l440gx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) module_exit(cleanup_l440gx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_DESCRIPTION("MTD map driver for BIOS chips on Intel L440GX motherboards");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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