^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2000 Nicolas Pitre <nico@fluxnic.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This code is GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct mtd_info *dc21285_mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_ARCH_NETWINDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * This is really ugly, but it seams to be the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * realiable way to do it, as the cpld state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * is unpredictible. So we have a 25us penalty per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * write access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void nw_en_write(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * we want to write a bit pattern XXX1 to Xilinx to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * the write gate, which will be open for about the next 2ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) raw_spin_lock_irqsave(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * let the ISA bus to catch on...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) udelay(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define nw_en_write() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static map_word dc21285_read8(struct map_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val.x[0] = *(uint8_t*)(map->virt + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static map_word dc21285_read16(struct map_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val.x[0] = *(uint16_t*)(map->virt + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static map_word dc21285_read32(struct map_info *map, unsigned long ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) map_word val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val.x[0] = *(uint32_t*)(map->virt + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) memcpy(to, (void*)(map->virt + from), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (machine_is_netwinder())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) nw_en_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *CSR_ROMWRITEREG = adr & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) adr &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *(uint8_t*)(map->virt + adr) = d.x[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (machine_is_netwinder())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) nw_en_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *CSR_ROMWRITEREG = adr & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) adr &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *(uint16_t*)(map->virt + adr) = d.x[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (machine_is_netwinder())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) nw_en_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *(uint32_t*)(map->virt + adr) = d.x[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const void *from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) map_word d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) d.x[0] = *((uint32_t*)from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dc21285_write32(map, d, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) from += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) to += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const void *from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) map_word d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) d.x[0] = *((uint16_t*)from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dc21285_write16(map, d, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) from += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) to += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) map_word d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) d.x[0] = *((uint8_t*)from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dc21285_write8(map, d, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) from++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) to++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct map_info dc21285_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "DC21285 flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .phys = NO_XIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = 16*1024*1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .copy_from = dc21285_copy_from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Partition stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const probes[] = { "RedBoot", "cmdlinepart", NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __init init_dc21285(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Determine bankwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) switch (*CSR_SA110_CNTL & (3<<14)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case SA110_CNTL_ROMWIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dc21285_map.bankwidth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dc21285_map.read = dc21285_read8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dc21285_map.write = dc21285_write8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dc21285_map.copy_to = dc21285_copy_to_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case SA110_CNTL_ROMWIDTH_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dc21285_map.bankwidth = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dc21285_map.read = dc21285_read16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dc21285_map.write = dc21285_write16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dc21285_map.copy_to = dc21285_copy_to_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case SA110_CNTL_ROMWIDTH_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dc21285_map.bankwidth = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dc21285_map.read = dc21285_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dc21285_map.write = dc21285_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dc21285_map.copy_to = dc21285_copy_to_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) printk (KERN_ERR "DC21285 flash: undefined bankwidth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dc21285_map.bankwidth*8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Let's map the flash area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dc21285_map.virt = ioremap(DC21285_FLASH, 16*1024*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!dc21285_map.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk("Failed to ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (machine_is_ebsa285()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!dc21285_mtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) iounmap(dc21285_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dc21285_mtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mtd_device_parse_register(dc21285_mtd, probes, NULL, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if(machine_is_ebsa285()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Flash timing is determined with bits 19-16 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * CSR_SA110_CNTL. The value is the number of wait cycles, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 0 for 16 cycles (the default). Cycles are 20 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Here we use 7 for 140 ns flash chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* access time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* burst time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* tristate time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void __exit cleanup_dc21285(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mtd_device_unregister(dc21285_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) map_destroy(dc21285_mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) iounmap(dc21285_map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) module_init(init_dc21285);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) module_exit(cleanup_dc21285);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_AUTHOR("Nicolas Pitre <nico@fluxnic.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_DESCRIPTION("MTD map driver for DC21285 boards");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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