^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * support for LPDDR2-NVM PCM memories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright © 2012 Micron Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Vincenzo Aliberti <vincenzo.aliberti@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Domenico Manna <domenico.manna@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Many thanks to Andrea Vigilante for initial enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ERASE_BLOCKSIZE (0x00020000/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WRITE_BUFFSIZE (0x00000400/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OW_BASE_ADDRESS 0x00000000 /* OW offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BUS_WIDTH 0x00000020 /* x32 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PFOW symbols address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PFOW_QUERY_STRING_P (0x0000/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PFOW_QUERY_STRING_F (0x0002/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PFOW_QUERY_STRING_O (0x0004/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PFOW_QUERY_STRING_W (0x0006/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* OW registers address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMD_CODE_OFS (0x0080/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMD_DATA_OFS (0x0084/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMD_ADD_L_OFS (0x0088/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMD_ADD_H_OFS (0x008A/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPR_L_OFS (0x0090/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPR_H_OFS (0x0092/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD_EXEC_OFS (0x00C0/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STATUS_REG_OFS (0x00CC/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PRG_BUFFER_OFS (0x0010/2) /* in Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Datamask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MR_CFGMASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SR_OK_DATAMASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* LPDDR2-NVM Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPDDR2_NVM_LOCK 0x0061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPDDR2_NVM_UNLOCK 0x0062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LPDDR2_NVM_SW_PROGRAM 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPDDR2_NVM_SW_OVERWRITE 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LPDDR2_NVM_BUF_PROGRAM 0x00E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LPDDR2_NVM_BUF_OVERWRITE 0x00EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPDDR2_NVM_ERASE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* LPDDR2-NVM Registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LPDDR2_MODE_REG_DATA 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LPDDR2_MODE_REG_CFG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Internal Type Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * pcm_int_data contains memory controller details:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @reg_data : LPDDR2_MODE_REG_DATA register address after remapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @reg_cfg : LPDDR2_MODE_REG_CFG register address after remapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pcm_int_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *ctl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static DEFINE_MUTEX(lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Build a map_word starting from an u_long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline map_word build_map_word(u_long myword)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) map_word val = { {0} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val.x[0] = myword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Build Mode Register Configuration DataMask based on device bus-width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline u_int build_mr_cfgmask(u_int bus_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u_int val = MR_CFGMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (bus_width == 0x0004) /* x32 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val = val << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Build Status Register OK DataMask based on device bus-width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline u_int build_sr_ok_datamask(u_int bus_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u_int val = SR_OK_DATAMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (bus_width == 0x0004) /* x32 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = (val << 16)+val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Evaluates Overlay Window Control Registers address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline u_long ow_reg_add(struct map_info *map, u_long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u_long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pcm_int_data *pcm_data = map->fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = map->pfow_base + offset*pcm_data->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Enable lpddr2-nvm Overlay Window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * used by device commands as well as uservisible resources like Device Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Register, Device ID, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void ow_enable(struct map_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pcm_int_data *pcm_data = map->fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Disable lpddr2-nvm Overlay Window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * used by device commands as well as uservisible resources like Device Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Register, Device ID, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void ow_disable(struct map_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pcm_int_data *pcm_data = map->fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Execute lpddr2-nvm operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int lpddr2_nvm_do_op(struct map_info *map, u_long cmd_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u_long cmd_data, u_long cmd_add, u_long cmd_mpr, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) map_word add_l = { {0} }, add_h = { {0} }, mpr_l = { {0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mpr_h = { {0} }, data_l = { {0} }, cmd = { {0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) exec_cmd = { {0} }, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) map_word data_h = { {0} }; /* only for 2x x16 devices stacked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u_long i, status_reg, prg_buff_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pcm_int_data *pcm_data = map->fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Builds low and high words for OW Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) add_l.x[0] = cmd_add & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) add_h.x[0] = (cmd_add >> 16) & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mpr_l.x[0] = cmd_mpr & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mpr_h.x[0] = (cmd_mpr >> 16) & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cmd.x[0] = cmd_code & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) exec_cmd.x[0] = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) data_l.x[0] = cmd_data & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) data_h.x[0] = (cmd_data >> 16) & 0x0000FFFF; /* only for 2x x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Set Overlay Window Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) map_write(map, data_l, ow_reg_add(map, CMD_DATA_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) map_write(map, data_h, ow_reg_add(map, CMD_DATA_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Fill Program Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if ((cmd_code == LPDDR2_NVM_BUF_PROGRAM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (cmd_code == LPDDR2_NVM_BUF_OVERWRITE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) prg_buff_ofs = (map_read(map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ow_reg_add(map, PRG_BUFFER_OFS))).x[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (i = 0; i < cmd_mpr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) map_write(map, build_map_word(buf[i]), map->pfow_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) prg_buff_ofs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Command Execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (pcm_data->bus_width == 0x0004) /* 2x16 devices stacked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Status Register Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sr = map_read(map, ow_reg_add(map, STATUS_REG_OFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) status_reg = sr.x[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sr = map_read(map, ow_reg_add(map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) STATUS_REG_OFS) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) status_reg += sr.x[0] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } while ((status_reg & sr_ok_datamask) != sr_ok_datamask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return (((status_reg & sr_ok_datamask) == sr_ok_datamask) ? 0 : -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Execute lpddr2-nvm operations @ block level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int lpddr2_nvm_do_block_op(struct mtd_info *mtd, loff_t start_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint64_t len, u_char block_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct map_info *map = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u_long add, end_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mutex_lock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ow_enable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) add = start_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) end_add = add + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = lpddr2_nvm_do_op(map, block_op, 0x00, add, add, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) add += mtd->erasesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } while (add < end_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ow_disable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mutex_unlock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * verify presence of PFOW string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int lpddr2_nvm_pfow_present(struct map_info *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) map_word pfow_val[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mutex_lock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ow_enable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Load string from array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Verify the string loaded vs expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!map_word_equal(map, build_map_word('P'), pfow_val[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!map_word_equal(map, build_map_word('F'), pfow_val[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!map_word_equal(map, build_map_word('O'), pfow_val[2]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!map_word_equal(map, build_map_word('W'), pfow_val[3]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ow_disable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mutex_unlock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * lpddr2_nvm driver read method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int lpddr2_nvm_read(struct mtd_info *mtd, loff_t start_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) size_t len, size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct map_info *map = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mutex_lock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) map_copy_from(map, buf, start_add, *retlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_unlock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * lpddr2_nvm driver write method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int lpddr2_nvm_write(struct mtd_info *mtd, loff_t start_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) size_t len, size_t *retlen, const u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct map_info *map = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pcm_int_data *pcm_data = map->fldrv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u_long add, current_len, tot_len, target_len, my_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u_char *write_buf = (u_char *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mutex_lock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ow_enable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Set start value for the variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) add = start_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) target_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tot_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) while (tot_len < target_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!(IS_ALIGNED(add, mtd->writesize))) { /* do sw program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) my_data = write_buf[tot_len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) my_data += (write_buf[tot_len+1]) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) my_data += (write_buf[tot_len+2]) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) my_data += (write_buf[tot_len+3]) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_SW_OVERWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) my_data, add, 0x00, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) add += pcm_data->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tot_len += pcm_data->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else { /* do buffer program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) current_len = min(target_len - tot_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (u_long) mtd->writesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_BUF_OVERWRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x00, add, current_len, write_buf + tot_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) add += current_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tot_len += current_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *retlen = tot_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ow_disable(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mutex_unlock(&lpdd2_nvm_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * lpddr2_nvm driver erase method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) LPDDR2_NVM_ERASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * lpddr2_nvm driver unlock method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int lpddr2_nvm_unlock(struct mtd_info *mtd, loff_t start_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uint64_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * lpddr2_nvm driver lock method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint64_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct mtd_info lpddr2_nvm_mtd_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .type = MTD_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .writesize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ._read = lpddr2_nvm_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ._write = lpddr2_nvm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ._erase = lpddr2_nvm_erase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ._unlock = lpddr2_nvm_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ._lock = lpddr2_nvm_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * lpddr2_nvm driver probe method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int lpddr2_nvm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct map_info *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct resource *add_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct resource *control_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct pcm_int_data *pcm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Allocate memory control_regs data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pcm_data = devm_kzalloc(&pdev->dev, sizeof(*pcm_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!pcm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pcm_data->bus_width = BUS_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Allocate memory for map_info & mtd_info data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) map = devm_kzalloc(&pdev->dev, sizeof(*map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mtd = devm_kzalloc(&pdev->dev, sizeof(*mtd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* lpddr2_nvm address range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) add_range = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Populate map_info data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *map = (struct map_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .virt = devm_ioremap_resource(&pdev->dev, add_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = pdev->dev.init_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .phys = add_range->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .size = resource_size(add_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .bankwidth = pcm_data->bus_width / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .pfow_base = OW_BASE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .fldrv_priv = pcm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (IS_ERR(map->virt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return PTR_ERR(map->virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) simple_map_init(map); /* fill with default methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) control_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pcm_data->ctl_regs = devm_ioremap_resource(&pdev->dev, control_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (IS_ERR(pcm_data->ctl_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return PTR_ERR(pcm_data->ctl_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Populate mtd_info data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *mtd = lpddr2_nvm_mtd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mtd->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mtd->name = pdev->dev.init_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mtd->priv = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mtd->size = resource_size(add_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Verify the presence of the device looking for PFOW string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!lpddr2_nvm_pfow_present(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pr_err("device not recognized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Parse partitions and register the MTD device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return mtd_device_register(mtd, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * lpddr2_nvm driver remove method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int lpddr2_nvm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return mtd_device_unregister(dev_get_drvdata(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Initialize platform_driver data structure for lpddr2_nvm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct platform_driver lpddr2_nvm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "lpddr2_nvm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .probe = lpddr2_nvm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .remove = lpddr2_nvm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) module_platform_driver(lpddr2_nvm_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_AUTHOR("Vincenzo Aliberti <vincenzo.aliberti@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DESCRIPTION("MTD driver for LPDDR2-NVM PCM memories");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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