Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Vignesh Raghavendra <vigneshr@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mtd/cfi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mtd/hyperbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mux/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AM654_HBMC_CALIB_COUNT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct am654_hbmc_device_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct completion rx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	phys_addr_t device_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct hyperbus_ctlr *ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct am654_hbmc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct hyperbus_ctlr ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct hyperbus_device hbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct mux_control *mux_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static int am654_hbmc_calibrate(struct hyperbus_device *hbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct map_info *map = &hbdev->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct cfi_private cfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int count = AM654_HBMC_CALIB_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int pass_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	cfi.interleave = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	cfi.device_type = CFI_DEVICETYPE_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	cfi_send_gen_cmd(0xF0, 0, 0, map, &cfi, cfi.device_type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	cfi_send_gen_cmd(0x98, 0x55, 0, map, &cfi, cfi.device_type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		ret = cfi_qry_present(map, 0, &cfi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			pass_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			pass_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		if (pass_count == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	cfi_qry_mode_off(0, map, &cfi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void am654_hbmc_dma_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct am654_hbmc_device_priv *priv = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	complete(&priv->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int am654_hbmc_dma_read(struct am654_hbmc_device_priv *priv, void *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			       unsigned long from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct dma_chan *rx_chan = priv->rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dma_addr_t dma_dst, dma_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (!priv->rx_chan || !virt_addr_valid(to) || object_is_on_stack(to))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	dma_dst = dma_map_single(rx_chan->device->dev, to, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (dma_mapping_error(rx_chan->device->dev, dma_dst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		dev_dbg(priv->ctlr->dev, "DMA mapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dma_src = priv->device_base + from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	tx = dmaengine_prep_dma_memcpy(rx_chan, dma_dst, dma_src, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		dev_err(priv->ctlr->dev, "device_prep_dma_memcpy error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		goto unmap_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	reinit_completion(&priv->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	tx->callback = am654_hbmc_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tx->callback_param = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	cookie = dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		dev_err(priv->ctlr->dev, "dma_submit_error %d\n", cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		goto unmap_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	dma_async_issue_pending(rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (!wait_for_completion_timeout(&priv->rx_dma_complete,  msecs_to_jiffies(len + 1000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		dmaengine_terminate_sync(rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dev_err(priv->ctlr->dev, "DMA wait_for_completion_timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unmap_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	dma_unmap_single(rx_chan->device->dev, dma_dst, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void am654_hbmc_read(struct hyperbus_device *hbdev, void *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			    unsigned long from, ssize_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct am654_hbmc_device_priv *priv = hbdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (len < SZ_1K || am654_hbmc_dma_read(priv, to, from, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		memcpy_fromio(to, hbdev->map.virt + from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct hyperbus_ops am654_hbmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.calibrate = am654_hbmc_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.copy_from = am654_hbmc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int am654_hbmc_request_mmap_dma(struct am654_hbmc_device_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dma_cap_set(DMA_MEMCPY, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	rx_chan = dma_request_chan_by_mask(&mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (IS_ERR(rx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (PTR_ERR(rx_chan) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_dbg(priv->ctlr->dev, "No DMA channel available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	priv->rx_chan = rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	init_completion(&priv->rx_dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int am654_hbmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct am654_hbmc_device_priv *dev_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct am654_hbmc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	priv->hbdev.np = of_get_next_child(np, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ret = of_address_to_resource(priv->hbdev.np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (of_property_read_bool(dev->of_node, "mux-controls")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		struct mux_control *control = devm_mux_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (IS_ERR(control))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			return PTR_ERR(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = mux_control_select(control, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			dev_err(dev, "Failed to select HBMC mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		priv->mux_ctrl = control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	priv->hbdev.map.size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	priv->hbdev.map.virt = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (IS_ERR(priv->hbdev.map.virt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return PTR_ERR(priv->hbdev.map.virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	priv->ctlr.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	priv->ctlr.ops = &am654_hbmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	priv->hbdev.ctlr = &priv->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	dev_priv = devm_kzalloc(dev, sizeof(*dev_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!dev_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		goto disable_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	priv->hbdev.priv = dev_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	dev_priv->device_base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_priv->ctlr = &priv->ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = am654_hbmc_request_mmap_dma(dev_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		goto disable_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = hyperbus_register_device(&priv->hbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(dev, "failed to register controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto release_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) release_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (dev_priv->rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dma_release_channel(dev_priv->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) disable_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (priv->mux_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		mux_control_deselect(priv->mux_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int am654_hbmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct am654_hbmc_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct am654_hbmc_device_priv *dev_priv = priv->hbdev.priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = hyperbus_unregister_device(&priv->hbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (priv->mux_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		mux_control_deselect(priv->mux_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (dev_priv->rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dma_release_channel(dev_priv->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id am654_hbmc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.compatible = "ti,am654-hbmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	{ /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DEVICE_TABLE(of, am654_hbmc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_driver am654_hbmc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.probe = am654_hbmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.remove = am654_hbmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.name = "hbmc-am654",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.of_match_table = am654_hbmc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) module_platform_driver(am654_hbmc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DESCRIPTION("HBMC driver for AM654 SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_ALIAS("platform:hbmc-am654");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");