^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SMI (Serial Memory Controller) device driver for Serial NOR Flash on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPEAr platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The serial nor interface is largely based on m25p80.c, however the SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * interface has been replaced by SMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright © 2010 STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ashish Priyadarshi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mtd/spear_smi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* SMI clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* MAX time out to safely come out of a erase or write busy conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMI_PROBE_TIMEOUT (HZ / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMI_MAX_TIME_OUT (3 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* timeout for command completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMI_CMD_TIMEOUT (HZ / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* registers of smi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SMI_CR1 0x0 /* SMI control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SMI_CR2 0x4 /* SMI control register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SMI_SR 0x8 /* SMI status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SMI_TR 0xC /* SMI transmit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SMI_RR 0x10 /* SMI receive register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* defines for control_reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BANK_EN (0xF << 0) /* enables all banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SW_MODE (0x1 << 28) /* enables SW Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WB_MODE (0x1 << 29) /* Write Burst Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FAST_MODE (0x1 << 15) /* Fast Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HOLD1 (0x1 << 16) /* Clock Hold period selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* defines for control_reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SEND (0x1 << 7) /* Send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RD_STATUS_REG (0x1 << 10) /* reads status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WE (0x1 << 11) /* Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TX_LEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RX_LEN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BANK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* defines for status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SR_WIP 0x1 /* Write in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SR_WEL 0x2 /* Write enable latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SR_BP0 0x4 /* Block protect 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SR_BP1 0x8 /* Block protect 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SR_BP2 0x10 /* Block protect 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SR_SRWD 0x80 /* SR write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TFF 0x100 /* Transfer Finished Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WCF 0x200 /* Transfer Finished Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ERF1 0x400 /* Forbidden Write Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ERF2 0x800 /* Forbidden Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* flash opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OPCODE_RDID 0x9f /* Read JEDEC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Flash Device Ids maintenance section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* data structure to maintain flash ids from different vendors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct flash_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long sectorsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long size_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FLASH_ID(n, es, id, psize, ssize, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .erase_cmd = es, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .device_id = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pagesize = psize, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .sectorsize = ssize, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .size_in_bytes = size \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct flash_device flash_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FLASH_ID("atmel 25f512" , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Define spear specific structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct spear_snor_flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * struct spear_smi - Structure for SMI Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @clk: functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @status: current status register of SMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @lock: lock to prevent parallel access of SMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @io_base: base address for registers of SMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @pdev: platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @cmd_complete: queue to wait for command completion of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @num_flashes: number of flashes actually present on board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @flash: separate structure for each Serial NOR-flash attached to SMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct spear_smi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) wait_queue_head_t cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 num_flashes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * struct spear_snor_flash - Structure for Serial NOR Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @dev_id: Device ID of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @lock: lock to manage flash read, write and erase operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @mtd: MTD info for each NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @num_parts: Total number of partition in each bank of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @parts: Partition info for each bank of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @page_size: Page size of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @base_addr: Base address of NOR-flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @erase_cmd: erase command may vary on different flash types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @fast_mode: flash supports read in fast mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct spear_snor_flash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct mtd_info mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 num_parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct mtd_partition *parts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 fast_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return container_of(mtd, struct spear_snor_flash, mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * spear_smi_read_sr - Read status register of flash through SMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @dev: structure of SMI information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @bank: bank to which flash is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * This routine will return the status register of the flash chip present at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * given bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int spear_smi_read_sr(struct spear_smi *dev, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 ctrlreg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev->status = 0; /* Will be set in interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ctrlreg1 = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* program smi in hw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* performing a rsr instruction in hw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* wait for tff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = wait_event_interruptible_timeout(dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev->status & TFF, SMI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* copy dev->status (lower 16 bits) in order to release lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = dev->status & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* restore the ctrl regs state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(ctrlreg1, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(0, dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * spear_smi_wait_till_ready - wait till flash is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @dev: structure of SMI information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @bank: flash corresponding to this bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @timeout: timeout for busy wait condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * This routine checks for WIP (write in progress) bit in Status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * If successful the routine returns 0 else -EBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) finish = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status = spear_smi_read_sr(dev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (status == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) continue; /* try till finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else if (!(status & SR_WIP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } while (!time_after_eq(jiffies, finish));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * spear_smi_int_handler - SMI Interrupt Handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @irq: irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @dev_id: structure of SMI device, embedded in dev_id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * The handler clears all interrupt conditions and records the status in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * dev->status which is used by the driver later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static irqreturn_t spear_smi_int_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct spear_smi *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) status = readl(dev->io_base + SMI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (unlikely(!status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* clear all interrupt conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) writel(0, dev->io_base + SMI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* copy the status register in dev->status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev->status |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* send the completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) wake_up_interruptible(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * spear_smi_hw_init - initializes the smi controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @dev: structure of smi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * this routine initializes the smi controller wit the default values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void spear_smi_hw_init(struct spear_smi *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 prescale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rate = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* functional clock of smi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) prescale = DIV_ROUND_UP(rate, dev->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * setting the standard values, fast mode, prescaler for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* clear all interrupt conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(0, dev->io_base + SMI_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel(val, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * get_flash_index - match chip id from a flash list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @flash_id: a valid nor flash chip id obtained from board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * try to validate the chip id by matching from a list, if not found then simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * returns negative. In case of success returns index in to the flash devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int get_flash_index(u32 flash_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Matches chip-id to entire list of 'serial-nor flash' ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (index = 0; index < ARRAY_SIZE(flash_devices); index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (flash_devices[index].device_id == flash_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Memory chip is not listed and not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * spear_smi_write_enable - Enable the flash to do write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @dev: structure of SMI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @bank: enable write for flash connected to this bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Set write enable latch with Write Enable command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int spear_smi_write_enable(struct spear_smi *dev, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 ctrlreg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev->status = 0; /* Will be set in interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctrlreg1 = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* program smi in h/w mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* give the flash, write enable command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = wait_event_interruptible_timeout(dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev->status & TFF, SMI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* restore the ctrl regs state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writel(ctrlreg1, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel(0, dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "smi controller failed on write enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* check whether write mode status is set for required bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (dev->status & (1 << (bank + WM_SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(&dev->pdev->dev, "couldn't enable write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 *x = (u8 *)&cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) x[0] = flash->erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) x[1] = offset >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) x[2] = offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) x[3] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * spear_smi_erase_sector - erase one sector of flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @dev: structure of SMI information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @command: erase command to be send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @bank: bank to which this command needs to be send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @bytes: size of command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Erase one sector of flash memory at offset ``offset'' which is any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * address within the sector which should be erased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Returns 0 if successful, non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int spear_smi_erase_sector(struct spear_smi *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 bank, u32 command, u32 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 ctrlreg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = spear_smi_write_enable(dev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ctrlreg1 = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* send command in sw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) writel(command, dev->io_base + SMI_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = wait_event_interruptible_timeout(dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev->status & TFF, SMI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&dev->pdev->dev, "sector erase failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = 0; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* restore ctrl regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel(ctrlreg1, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writel(0, dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * spear_mtd_erase - perform flash erase operation as requested by user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * @mtd: Provides the memory characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * @e_info: Provides the erase information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Erase an address range on the flash chip. The address range may extend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * one or more erase sectors. Return an error is there is a problem erasing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct spear_snor_flash *flash = get_flash_data(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct spear_smi *dev = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 addr, command, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!flash || !dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bank = flash->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (bank > dev->num_flashes - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(&dev->pdev->dev, "Invalid Bank Num");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) addr = e_info->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) len = e_info->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mutex_lock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* now erase sectors in loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) command = get_sector_erase_cmd(flash, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* preparing the command for flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = spear_smi_erase_sector(dev, bank, command, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) addr += mtd->erasesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) len -= mtd->erasesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * spear_mtd_read - performs flash read operation as requested by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @mtd: MTD information of the memory bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @from: Address from which to start read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @len: Number of bytes to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @retlen: Fills the Number of bytes actually read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @buf: Fills this after reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Read an address range from the flash chip. The address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * may be any size provided it is within the physical boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * Returns 0 on success, non zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) size_t *retlen, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct spear_snor_flash *flash = get_flash_data(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct spear_smi *dev = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void __iomem *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 ctrlreg1, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!flash || !dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (flash->bank > dev->num_flashes - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(&dev->pdev->dev, "Invalid Bank Num");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* select address as per bank number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) src = flash->base_addr + from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_lock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* wait till previous write/erase is done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* put smi in hw mode not wbt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ctrlreg1 = val = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val &= ~(SW_MODE | WB_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (flash->fast_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) val |= FAST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(val, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) memcpy_fromio(buf, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* restore ctrl reg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) writel(ctrlreg1, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * The purpose of this function is to ensure a memcpy_toio() with byte writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * only. Its structure is inspired from the ARM implementation of _memcpy_toio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * which also does single byte writes but cannot be used here as this is just an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * implementation detail and not part of the API. Not mentioning the comment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * stating that _memcpy_toio() should be optimized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void spear_smi_memcpy_toio_b(volatile void __iomem *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const void *src, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) const unsigned char *from = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writeb(*from, dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) from++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dest++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void __iomem *dest, const void *src, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 ctrlreg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* wait until finished previous write command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* put smi in write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = spear_smi_write_enable(dev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* put smi in hw, write burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ctrlreg1 = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * In Write Burst mode (WB_MODE), the specs states that writes must be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * - incremental
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * - of the same size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * The ARM implementation of memcpy_toio() will optimize the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * I/O by using as much 4-byte writes as possible, surrounded by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * 2-byte/1-byte access if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * - the destination is not 4-byte aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * - the length is not a multiple of 4-byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Avoid this alternance of write access size by using our own 'byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * access' helper if at least one of the two conditions above is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (IS_ALIGNED(len, sizeof(u32)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) IS_ALIGNED((uintptr_t)dest, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) memcpy_toio(dest, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) spear_smi_memcpy_toio_b(dest, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writel(ctrlreg1, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * spear_mtd_write - performs write operation as requested by the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @mtd: MTD information of the memory bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @to: Address to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @len: Number of bytes to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @retlen: Number of bytes actually wrote.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @buf: Buffer from which the data to be taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Write an address range to the flash chip. Data must be written in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * flash_page_size chunks. The address range may be any size provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * it is within the physical boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Returns 0 on success, non zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) size_t *retlen, const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct spear_snor_flash *flash = get_flash_data(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct spear_smi *dev = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) void __iomem *dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 page_offset, page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!flash || !dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (flash->bank > dev->num_flashes - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&dev->pdev->dev, "Invalid Bank Num");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* select address as per bank number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dest = flash->base_addr + to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mutex_lock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) page_offset = (u32)to % flash->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* do if all the bytes fit onto one page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (page_offset + len <= flash->page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *retlen += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* the size of data remaining on the first page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) page_size = flash->page_size - page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto err_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) *retlen += page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* write everything in pagesize chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) for (i = page_size; i < len; i += page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) page_size = len - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (page_size > flash->page_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) page_size = flash->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = spear_smi_cpy_toio(dev, flash->bank, dest + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) buf + i, page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *retlen += page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * spear_smi_probe_flash - Detects the NOR Flash chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * @dev: structure of SMI information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * @bank: bank on which flash must be probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * This routine will check whether there exists a flash chip on a given memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * bank ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Return index of the probed flash in flash devices structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev->status = 0; /* Will be set in interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* put smi in sw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) val = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) writel(val | SW_MODE, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* send readid command in sw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) writel(OPCODE_RDID, dev->io_base + SMI_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) (3 << RX_LEN_SHIFT) | TFIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) writel(val, dev->io_base + SMI_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* wait for TFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = wait_event_interruptible_timeout(dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev->status & TFF, SMI_CMD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto err_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* get memory chip id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val = readl(dev->io_base + SMI_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) val &= 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = get_flash_index(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) err_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* clear sw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) val = readl(dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int spear_smi_probe_config_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct device_node *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) of_property_read_u32(np, "clock-rate", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pdata->clk_rate = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pdata->board_flash_info = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sizeof(*pdata->board_flash_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!pdata->board_flash_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Fill structs for each subnode (flash device) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) for_each_child_of_node(np, pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pdata->np[i] = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Read base-addr and size from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) addr = of_get_property(pp, "reg", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pdata->board_flash_info->size = be32_to_cpup(&addr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (of_get_property(pp, "st,smi-fast-mode", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pdata->board_flash_info->fast_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pdata->num_flashes = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int spear_smi_probe_config_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int spear_smi_setup_banks(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 bank, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct spear_smi *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct spear_smi_flash_info *flash_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct spear_smi_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct spear_snor_flash *flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct mtd_partition *parts = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int flash_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (bank > pdata->num_flashes - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) flash_info = &pdata->board_flash_info[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!flash_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) flash = devm_kzalloc(&pdev->dev, sizeof(*flash), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) flash->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) flash->fast_mode = flash_info->fast_mode ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mutex_init(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* verify whether nor flash is really present on board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) flash_index = spear_smi_probe_flash(dev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (flash_index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return flash_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* map the memory for nor flash chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) flash->base_addr = devm_ioremap(&pdev->dev, flash_info->mem_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) flash_info->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!flash->base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev->flash[bank] = flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) flash->mtd.priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (flash_info->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) flash->mtd.name = flash_info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) flash->mtd.name = flash_devices[flash_index].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) flash->mtd.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) mtd_set_of_node(&flash->mtd, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) flash->mtd.type = MTD_NORFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) flash->mtd.writesize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) flash->mtd.flags = MTD_CAP_NORFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) flash->mtd.size = flash_info->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) flash->mtd.erasesize = flash_devices[flash_index].sectorsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) flash->page_size = flash_devices[flash_index].pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) flash->mtd.writebufsize = flash->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) flash->erase_cmd = flash_devices[flash_index].erase_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) flash->mtd._erase = spear_mtd_erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) flash->mtd._read = spear_mtd_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) flash->mtd._write = spear_mtd_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) flash->dev_id = flash_devices[flash_index].device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) flash->mtd.name, flash->mtd.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) flash->mtd.size / (1024 * 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) flash->mtd.erasesize, flash->mtd.erasesize / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #ifndef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (flash_info->partitions) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) parts = flash_info->partitions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) count = flash_info->nr_partitions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = mtd_device_register(&flash->mtd, parts, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * spear_smi_probe - Entry routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * @pdev: platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * This is the first routine which gets invoked during booting and does all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * initialization/allocation work. The routine looks for available memory banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * and do proper init for any found one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Returns 0 on success, non zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int spear_smi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct spear_smi_plat_data *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct spear_smi *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct resource *smi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pdev->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = spear_smi_probe_config_dt(pdev, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev->io_base = devm_ioremap_resource(&pdev->dev, smi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (IS_ERR(dev->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = PTR_ERR(dev->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev->clk_rate = pdata->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (dev->clk_rate > SMI_MAX_CLOCK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev->clk_rate = SMI_MAX_CLOCK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev->num_flashes = pdata->num_flashes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (dev->num_flashes > MAX_NUM_FLASH_CHIP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(&pdev->dev, "exceeding max number of flashes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev->num_flashes = MAX_NUM_FLASH_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = devm_request_irq(&pdev->dev, irq, spear_smi_int_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mutex_init(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) init_waitqueue_head(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) spear_smi_hw_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* loop for each serial nor-flash which is connected to smi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) for (i = 0; i < dev->num_flashes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = spear_smi_setup_banks(pdev, i, pdata->np[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(&dev->pdev->dev, "bank setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * spear_smi_remove - Exit routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * @pdev: platform device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * free all allocations and delete the partitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int spear_smi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct spear_smi *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct spear_snor_flash *flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dev_err(&pdev->dev, "dev is null\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* clean up for all nor flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) for (i = 0; i < dev->num_flashes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) flash = dev->flash[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* clean up mtd stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = mtd_device_unregister(&flash->mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(&pdev->dev, "error removing mtd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int spear_smi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct spear_smi *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (sdev && sdev->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) clk_disable_unprepare(sdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int spear_smi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct spear_smi *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (sdev && sdev->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = clk_prepare_enable(sdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spear_smi_hw_init(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static SIMPLE_DEV_PM_OPS(spear_smi_pm_ops, spear_smi_suspend, spear_smi_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct of_device_id spear_smi_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) { .compatible = "st,spear600-smi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) MODULE_DEVICE_TABLE(of, spear_smi_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static struct platform_driver spear_smi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .name = "smi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .bus = &platform_bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .of_match_table = of_match_ptr(spear_smi_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .pm = &spear_smi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .probe = spear_smi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .remove = spear_smi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) module_platform_driver(spear_smi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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