^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PMC551 PCI Mezzanine Ram Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Mark Ferrell <mferrell@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 1999,2000 Nortel Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This driver is intended to support the PMC551 PCI Ram device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * from Ramix Inc. The PMC551 is a PMC Mezzanine module for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * cPCI embedded systems. The device contains a single SROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * that initially programs the V370PDC chipset onboard the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * device, and various banks of DRAM/SDRAM onboard. This driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * implements this PCI Ram device as an MTD (Memory Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Device) so that it can be used to hold a file system, or for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * added swap space in embedded systems. Since the memory on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * this board isn't as fast as main memory we do not try to hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * it into main memory as that would simply reduce performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * on the system. Using it as a block device allows us to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * it as high speed swap or for a high speed disk device of some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * sort. Which becomes very useful on diskless systems in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * embedded market I might add.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Due to what I assume is more buggy SROM, the 64M PMC551 I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * have available claims that all 4 of its DRAM banks have 64MiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * of ram configured (making a grand total of 256MiB onboard).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This is slightly annoying since the BAR0 size reflects the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * aperture size, not the dram size, and the V370PDC supplies no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * other method for memory size discovery. This problem is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * mostly only relevant when compiled as a module, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * unloading of the module with an aperture size smaller than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * the ram will cause the driver to detect the onboard memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * size to be equal to the aperture size when the module is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * reloaded. Soooo, to help, the module supports an msize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * option to allow the specification of the onboard memory, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * an asize option, to allow the specification of the aperture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * size. The aperture must be equal to or less then the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * size, the driver will correct this if you screw it up. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * problem is not relevant for compiled in drivers as compiled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * in drivers only init once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Credits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Saeed Karamooz <saeed@ramix.com> of Ramix INC. for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * initial example code of how to initialize this device and for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * help with questions I had concerning operation of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Most of the MTD code for this driver was originally written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * for the slram.o module in the MTD drivers package which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * allows the mapping of system memory into an MTD device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Since the PMC551 memory module is accessed in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * fashion as system memory, the slram.c code became a very nice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * fit to the needs of this driver. All we added was PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * detection/initialization to the driver and automatically figure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * out the size via the PCI detection.o, later changes by Corey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Minyard set up the card to utilize a 1M sliding apature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Corey Minyard <minyard@nortelnetworks.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * * Modified driver to utilize a sliding aperture instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * mapping all memory into kernel space which turned out to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * be very wasteful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * * Located a bug in the SROM's initialization sequence that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * made the memory unusable, added a fix to code to touch up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the DRAM some.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Bugs/FIXMEs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * * MUST fix the init function to not spin on a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * waiting for it to set .. this does not safely handle busted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * devices that never reset the register correctly which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * cause the system to hang w/ a reboot being the only chance at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * recover. [sort of fixed, could be better]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * * Add I2C handling of the SROM so we can read the SROM's information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * about the aperture size. This should always accurately reflect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * onboard memory size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * * Comb the init routine. It's still a bit cludgy on a few things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMC551_VERSION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "Ramix PMC551 PCI Mezzanine Ram Driver. (C) 1999,2000 Nortel Networks.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCI_VENDOR_ID_V3_SEMI 0x11b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCI_DEVICE_ID_V3_SEMI_V370PDC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMC551_PCI_MEM_MAP0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMC551_PCI_MEM_MAP1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMC551_PCI_MEM_MAP_MAP_ADDR_MASK 0x3ff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMC551_PCI_MEM_MAP_APERTURE_MASK 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMC551_PCI_MEM_MAP_REG_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMC551_PCI_MEM_MAP_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMC551_SDRAM_MA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMC551_SDRAM_CMD 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMC551_DRAM_CFG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMC551_SYS_CTRL_REG 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMC551_DRAM_BLK0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMC551_DRAM_BLK1 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMC551_DRAM_BLK2 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMC551_DRAM_BLK3 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMC551_DRAM_BLK_GET_SIZE(x) (524288 << ((x >> 4) & 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMC551_DRAM_BLK_SET_COL_MUX(x, v) (((x) & ~0x00007000) | (((v) & 0x7) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMC551_DRAM_BLK_SET_ROW_MUX(x, v) (((x) & ~0x00000f00) | (((v) & 0xf) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mypriv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u_char *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 base_map0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 curr_map0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mtd_info *nextpmc551;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct mtd_info *pmc551list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int pmc551_point(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) size_t *retlen, void **virt, resource_size_t *phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int pmc551_erase(struct mtd_info *mtd, struct erase_info *instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mypriv *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 soff_hi; /* start address offset hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 eoff_hi, eoff_lo; /* end address offset hi/lo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u_char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) size_t retlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) printk(KERN_DEBUG "pmc551_erase(pos:%ld, len:%ld)\n", (long)instr->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (long)instr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) end = instr->addr + instr->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) eoff_hi = end & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) soff_hi = instr->addr & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) eoff_lo = end & (priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pmc551_point(mtd, instr->addr, instr->len, &retlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (soff_hi == eoff_hi || mtd->size == priv->asize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* The whole thing fits within one access, so just one shot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) will do it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) memset(ptr, 0xff, instr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* We have to do multiple writes to get all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) while (soff_hi != eoff_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) printk(KERN_DEBUG "pmc551_erase() soff_hi: %ld, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) memset(ptr, 0xff, priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (soff_hi + priv->asize >= mtd->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) soff_hi += priv->asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pmc551_point(mtd, (priv->base_map0 | soff_hi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->asize, &retlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) memset(ptr, 0xff, eoff_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) printk(KERN_DEBUG "pmc551_erase() done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int pmc551_point(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) size_t *retlen, void **virt, resource_size_t *phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mypriv *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 soff_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 soff_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) printk(KERN_DEBUG "pmc551_point(%ld, %ld)\n", (long)from, (long)len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) soff_hi = from & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) soff_lo = from & (priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Cheap hack optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (priv->curr_map0 != from) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_write_config_dword(priv->dev, PMC551_PCI_MEM_MAP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (priv->base_map0 | soff_hi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) priv->curr_map0 = soff_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *virt = priv->start + soff_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int pmc551_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) printk(KERN_DEBUG "pmc551_unpoint()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int pmc551_read(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) size_t * retlen, u_char * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct mypriv *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 soff_hi; /* start address offset hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 eoff_hi, eoff_lo; /* end address offset hi/lo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u_char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u_char *copyto = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) printk(KERN_DEBUG "pmc551_read(pos:%ld, len:%ld) asize: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (long)from, (long)len, (long)priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) end = from + len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) soff_hi = from & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) eoff_hi = end & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) eoff_lo = end & (priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pmc551_point(mtd, from, len, retlen, (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (soff_hi == eoff_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* The whole thing fits within one access, so just one shot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) will do it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) memcpy(copyto, ptr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) copyto += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* We have to do multiple writes to get all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) while (soff_hi != eoff_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) printk(KERN_DEBUG "pmc551_read() soff_hi: %ld, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) memcpy(copyto, ptr, priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) copyto += priv->asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (soff_hi + priv->asize >= mtd->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) soff_hi += priv->asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pmc551_point(mtd, soff_hi, priv->asize, retlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) memcpy(copyto, ptr, eoff_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) copyto += eoff_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) printk(KERN_DEBUG "pmc551_read() done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *retlen = copyto - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int pmc551_write(struct mtd_info *mtd, loff_t to, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) size_t * retlen, const u_char * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct mypriv *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 soff_hi; /* start address offset hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 eoff_hi, eoff_lo; /* end address offset hi/lo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u_char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const u_char *copyfrom = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) printk(KERN_DEBUG "pmc551_write(pos:%ld, len:%ld) asize:%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (long)to, (long)len, (long)priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) end = to + len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) soff_hi = to & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) eoff_hi = end & ~(priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) eoff_lo = end & (priv->asize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pmc551_point(mtd, to, len, retlen, (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (soff_hi == eoff_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* The whole thing fits within one access, so just one shot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) will do it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) memcpy(ptr, copyfrom, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) copyfrom += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* We have to do multiple writes to get all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) while (soff_hi != eoff_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) printk(KERN_DEBUG "pmc551_write() soff_hi: %ld, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) memcpy(ptr, copyfrom, priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) copyfrom += priv->asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (soff_hi >= mtd->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) soff_hi += priv->asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pmc551_point(mtd, soff_hi, priv->asize, retlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (void **)&ptr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) memcpy(ptr, copyfrom, eoff_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) copyfrom += eoff_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) printk(KERN_DEBUG "pmc551_write() done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *retlen = copyfrom - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Fixup routines for the V370PDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * PCI device ID 0x020011b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * This function basically kick starts the DRAM oboard the card and gets it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * ready to be used. Before this is done the device reads VERY erratic, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * much that it can crash the Linux 2.2.x series kernels when a user cat's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * /proc/pci .. though that is mainly a kernel bug in handling the PCI DEVSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * register. FIXME: stop spinning on registers .. must implement a timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * returns the size of the memory region found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int __init fixup_pmc551(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_MTD_PMC551_BUGFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 dram_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 size, dcmd, cfg, dtmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 cmd, tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 bcmd, counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Sanity Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Attempt to reset the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * FIXME: Stop Spinning registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* unlock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* read in old data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* bang the reset line up and down for a few */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bcmd &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) while (counter++ < 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bcmd |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) while (counter++ < 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bcmd |= (0x40 | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * Take care and turn off the memory on the device while we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * tweak the configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pci_write_config_word(dev, PCI_COMMAND, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Disable existing aperture before probing memory size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pci_read_config_dword(dev, PMC551_PCI_MEM_MAP0, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dtmp = (dcmd | PMC551_PCI_MEM_MAP_ENABLE | PMC551_PCI_MEM_MAP_REG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_write_config_dword(dev, PMC551_PCI_MEM_MAP0, dtmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Grab old BAR0 config so that we can figure out memory size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * This is another bit of kludge going on. The reason for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * redundancy is I am hoping to retain the original configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * previously assigned to the card by the BIOS or some previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * fixup routine in the kernel. So we read the old config into cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * then write all 1's to the memory space, read back the result into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * "size", and then write back all the old config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifndef CONFIG_MTD_PMC551_BUGFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) size = (size & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) size &= ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Get the size of the memory by reading all the DRAM size values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * and adding them up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * KLUDGE ALERT: the boards we are using have invalid column and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * row mux values. We fix them here, but this will break other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * memory configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) size = PMC551_DRAM_BLK_GET_SIZE(dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_write_config_dword(dev, PMC551_DRAM_BLK0, dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pci_read_config_dword(dev, PMC551_DRAM_BLK1, &dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) size += PMC551_DRAM_BLK_GET_SIZE(dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pci_write_config_dword(dev, PMC551_DRAM_BLK1, dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_read_config_dword(dev, PMC551_DRAM_BLK2, &dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) size += PMC551_DRAM_BLK_GET_SIZE(dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pci_write_config_dword(dev, PMC551_DRAM_BLK2, dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pci_read_config_dword(dev, PMC551_DRAM_BLK3, &dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) size += PMC551_DRAM_BLK_GET_SIZE(dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_write_config_dword(dev, PMC551_DRAM_BLK3, dram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Oops .. something went wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((size &= PCI_BASE_ADDRESS_MEM_MASK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #endif /* CONFIG_MTD_PMC551_BUGFIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if ((cfg & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Precharge Dram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_write_config_word(dev, PMC551_SDRAM_MA, 0x0400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x00bf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Wait until command has gone through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * FIXME: register spinning issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (counter++ > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } while ((PCI_COMMAND_IO) & cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Turn on auto refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * The loop is taken directly from Ramix's example code. I assume that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * this must be held high for some duration of time, but I can find no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * documentation refrencing the reasons why.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for (i = 1; i <= 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0df);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Make certain command has gone through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * FIXME: register spinning issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (counter++ > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } while ((PCI_COMMAND_IO) & cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pci_write_config_word(dev, PMC551_SDRAM_MA, 0x0020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Wait until command completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * FIXME: register spinning issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (counter++ > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } while ((PCI_COMMAND_IO) & cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pci_read_config_dword(dev, PMC551_DRAM_CFG, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dcmd |= 0x02000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pci_write_config_dword(dev, PMC551_DRAM_CFG, dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Check to make certain fast back-to-back, if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * then set it so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pci_read_config_word(dev, PCI_STATUS, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if ((cmd & PCI_COMMAND_FAST_BACK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) cmd |= PCI_COMMAND_FAST_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pci_write_config_word(dev, PCI_STATUS, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Check to make certain the DEVSEL is set correctly, this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * has a tendency to assert DEVSEL and TRDY when a write is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * to the memory when memory is read-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if ((cmd & PCI_STATUS_DEVSEL_MASK) != 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cmd &= ~PCI_STATUS_DEVSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pci_write_config_word(dev, PCI_STATUS, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Set to be prefetchable and put everything back based on old cfg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * it's possible that the reset of the V370PDC nuked the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cfg |= PCI_BASE_ADDRESS_MEM_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_write_config_dword( dev, PCI_BASE_ADDRESS_0, cfg );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Turn PCI memory and I/O bus access back on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pci_write_config_word(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Some screen fun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "0x%llx\n", (size < 1024) ? size : (size < 1048576) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) size >> 10 : size >> 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) (size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ((dcmd & (0x1 << 3)) == 0) ? "non-" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) (unsigned long long)pci_resource_start(dev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Check to see the state of the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) printk(KERN_DEBUG "pmc551: DRAM_BLK0 Flags: %s,%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "pmc551: DRAM_BLK0 Size: %d at %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "pmc551: DRAM_BLK0 Row MUX: %d, Col MUX: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (((0x1 << 0) & dcmd) == 0) ? "Off" : "On",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PMC551_DRAM_BLK_GET_SIZE(dcmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ((dcmd >> 9) & 0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pci_read_config_dword(dev, PMC551_DRAM_BLK1, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) printk(KERN_DEBUG "pmc551: DRAM_BLK1 Flags: %s,%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "pmc551: DRAM_BLK1 Size: %d at %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "pmc551: DRAM_BLK1 Row MUX: %d, Col MUX: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) (((0x1 << 0) & dcmd) == 0) ? "Off" : "On",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PMC551_DRAM_BLK_GET_SIZE(dcmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ((dcmd >> 9) & 0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pci_read_config_dword(dev, PMC551_DRAM_BLK2, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) printk(KERN_DEBUG "pmc551: DRAM_BLK2 Flags: %s,%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "pmc551: DRAM_BLK2 Size: %d at %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "pmc551: DRAM_BLK2 Row MUX: %d, Col MUX: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) (((0x1 << 0) & dcmd) == 0) ? "Off" : "On",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PMC551_DRAM_BLK_GET_SIZE(dcmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ((dcmd >> 9) & 0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pci_read_config_dword(dev, PMC551_DRAM_BLK3, &dcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) printk(KERN_DEBUG "pmc551: DRAM_BLK3 Flags: %s,%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "pmc551: DRAM_BLK3 Size: %d at %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "pmc551: DRAM_BLK3 Row MUX: %d, Col MUX: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) (((0x1 << 0) & dcmd) == 0) ? "Off" : "On",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PMC551_DRAM_BLK_GET_SIZE(dcmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ((dcmd >> 9) & 0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) printk(KERN_DEBUG "pmc551: Memory Access %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (((0x1 << 1) & cmd) == 0) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) printk(KERN_DEBUG "pmc551: I/O Access %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) (((0x1 << 0) & cmd) == 0) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pci_read_config_word(dev, PCI_STATUS, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) printk(KERN_DEBUG "pmc551: Devsel %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x000) ? "Fast" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x200) ? "Medium" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x400) ? "Slow" : "Invalid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) printk(KERN_DEBUG "pmc551: %sFast Back-to-Back\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ((PCI_COMMAND_FAST_BACK & cmd) == 0) ? "Not " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) printk(KERN_DEBUG "pmc551: EEPROM is under %s control\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "pmc551: System Control Register is %slocked to PCI access\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "pmc551: System Control Register is %slocked to EEPROM access\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) (bcmd & 0x1) ? "software" : "hardware",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) (bcmd & 0x20) ? "" : "un", (bcmd & 0x40) ? "" : "un");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Kernel version specific module stuffages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_AUTHOR("Mark Ferrell <mferrell@mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DESCRIPTION(PMC551_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Stuff these outside the ifdef so as to not bust compiled in driver support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int msize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int asize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) module_param(msize, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_PARM_DESC(msize, "memory size in MiB [1 - 1024]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) module_param(asize, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MODULE_PARM_DESC(asize, "aperture size, must be <= memsize [1-1024]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * PMC551 Card Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int __init init_pmc551(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct pci_dev *PCI_Device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct mypriv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (msize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) msize = (1 << (ffs(msize) - 1)) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (msize > (1 << 30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) printk(KERN_NOTICE "pmc551: Invalid memory size [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) msize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (asize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) asize = (1 << (ffs(asize) - 1)) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (asize > (1 << 30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) printk(KERN_NOTICE "pmc551: Invalid aperture size "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "[%d]\n", asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) printk(KERN_INFO PMC551_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * PCU-bus chipset probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if ((PCI_Device = pci_get_device(PCI_VENDOR_ID_V3_SEMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PCI_DEVICE_ID_V3_SEMI_V370PDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PCI_Device)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) printk(KERN_NOTICE "pmc551: Found PCI V370PDC at 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) (unsigned long long)pci_resource_start(PCI_Device, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * The PMC551 device acts VERY weird if you don't init it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * first. i.e. it will not correctly report devsel. If for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * some reason the sdram is in a wrote-protected state the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * device will DEVSEL when it is written to causing problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * with the oldproc.c driver in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * some kernels (2.2.*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if ((length = fixup_pmc551(PCI_Device)) <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) printk(KERN_NOTICE "pmc551: Cannot init SDRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * This is needed until the driver is capable of reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * onboard I2C SROM to discover the "real" memory size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (msize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) length = msize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk(KERN_NOTICE "pmc551: Using specified memory "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "size 0x%x\n", length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) msize = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) priv = kzalloc(sizeof(struct mypriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) kfree(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mtd->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) priv->dev = PCI_Device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (asize > length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) printk(KERN_NOTICE "pmc551: reducing aperture size to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "fit %dM\n", length >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) priv->asize = asize = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else if (asize == 0 || asize == length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) printk(KERN_NOTICE "pmc551: Using existing aperture "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "size %dM\n", length >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) priv->asize = asize = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) printk(KERN_NOTICE "pmc551: Using specified aperture "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "size %dM\n", asize >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) priv->asize = asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) priv->start = pci_iomap(PCI_Device, 0, priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!priv->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) printk(KERN_NOTICE "pmc551: Unable to map IO space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) kfree(mtd->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) kfree(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) printk(KERN_DEBUG "pmc551: setting aperture to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ffs(priv->asize >> 20) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->base_map0 = (PMC551_PCI_MEM_MAP_REG_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) | PMC551_PCI_MEM_MAP_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) | (ffs(priv->asize >> 20) - 1) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) priv->curr_map0 = priv->base_map0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pci_write_config_dword(priv->dev, PMC551_PCI_MEM_MAP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) priv->curr_map0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #ifdef CONFIG_MTD_PMC551_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) printk(KERN_DEBUG "pmc551: aperture set to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) (priv->base_map0 & 0xF0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mtd->size = msize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mtd->flags = MTD_CAP_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mtd->_erase = pmc551_erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mtd->_read = pmc551_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mtd->_write = pmc551_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mtd->_point = pmc551_point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mtd->_unpoint = pmc551_unpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mtd->type = MTD_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mtd->name = "PMC551 RAM board";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mtd->erasesize = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mtd->writesize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mtd->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (mtd_device_register(mtd, NULL, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) printk(KERN_NOTICE "pmc551: Failed to register new device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pci_iounmap(PCI_Device, priv->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) kfree(mtd->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) kfree(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Keep a reference as the mtd_device_register worked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pci_dev_get(PCI_Device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) printk(KERN_NOTICE "Registered pmc551 memory device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) printk(KERN_NOTICE "Mapped %dMiB of memory from 0x%p to 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) priv->asize >> 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) priv->start, priv->start + priv->asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) printk(KERN_NOTICE "Total memory is %d%sB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) (length < 1024) ? length :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) (length < 1048576) ? length >> 10 : length >> 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (length < 1024) ? "" : (length < 1048576) ? "Ki" : "Mi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) priv->nextpmc551 = pmc551list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pmc551list = mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Exited early, reference left over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_dev_put(PCI_Device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!pmc551list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) printk(KERN_NOTICE "pmc551: not detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) printk(KERN_NOTICE "pmc551: %d pmc551 devices loaded\n", found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * PMC551 Card Cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static void __exit cleanup_pmc551(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct mtd_info *mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct mypriv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) while ((mtd = pmc551list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pmc551list = priv->nextpmc551;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (priv->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) printk(KERN_DEBUG "pmc551: unmapping %dMiB starting at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "0x%p\n", priv->asize >> 20, priv->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) pci_iounmap(priv->dev, priv->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pci_dev_put(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) kfree(mtd->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mtd_device_unregister(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) kfree(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) printk(KERN_NOTICE "pmc551: %d pmc551 devices unloaded\n", found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) module_init(init_pmc551);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) module_exit(cleanup_pmc551);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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