^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Largely derived from at91_dataflash.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2003-2005 SAN People (Pty) Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * each chip, which may be used for double buffered I/O; but this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * doesn't (yet) use these for any kind of i/o overlap or prefetching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Sometimes DataFlash is packaged in MMC-format cards, although the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * MMC stack can't (yet?) distinguish between MMC and DataFlash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * protocols during enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* reads can bypass the buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OP_READ_CONTINUOUS 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OP_READ_PAGE 0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* group B requests can run even while status reports "busy" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OP_READ_STATUS 0xD7 /* group B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* move data between host and buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OP_READ_BUFFER1 0xD4 /* group B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OP_READ_BUFFER2 0xD6 /* group B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OP_WRITE_BUFFER1 0x84 /* group B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OP_WRITE_BUFFER2 0x87 /* group B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* erasing flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OP_ERASE_PAGE 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OP_ERASE_BLOCK 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* move data between buffer and flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OP_TRANSFER_BUF1 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OP_TRANSFER_BUF2 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OP_MREAD_BUFFER1 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OP_MREAD_BUFFER2 0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OP_MWERASE_BUFFER1 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OP_MWERASE_BUFFER2 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* write to buffer, then write-erase to flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OP_PROGRAM_VIA_BUF1 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OP_PROGRAM_VIA_BUF2 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* compare buffer to flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OP_COMPARE_BUF1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OP_COMPARE_BUF2 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* read flash to buffer, then write-erase to flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OP_REWRITE_VIA_BUF1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OP_REWRITE_VIA_BUF2 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* newer chips report JEDEC manufacturer and device IDs; chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * serial number and OTP bits; and per-sector writeprotect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OP_READ_ID 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OP_READ_SECURITY 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OP_WRITE_SECURITY_REVC 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OP_WRITE_SECURITY 0x9B /* revision D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CFI_MFR_ATMEL 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DATAFLASH_SHIFT_EXTID 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DATAFLASH_SHIFT_ID 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct dataflash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 command[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) char name[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned short page_offset; /* offset in flash address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int page_size; /* of bytes per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mtd_info mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct of_device_id dataflash_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .compatible = "atmel,at45", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .compatible = "atmel,dataflash", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_DEVICE_TABLE(of, dataflash_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* ......................................................................... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Return the status of the DataFlash device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline int dataflash_status(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* NOTE: at45db321c over 25 MHz wants to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * a dummy byte after the opcode...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return spi_w8r8(spi, OP_READ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Poll the DataFlash device until it is READY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * This usually takes 5-20 msec or so; more for sector erase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int dataflash_waitready(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) status = dataflash_status(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_dbg(&spi->dev, "status %d?\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (status & (1 << 7)) /* RDY/nBSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* ......................................................................... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Erase pages of flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct spi_transfer x = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned blocksize = priv->page_size << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_dbg(&spi->dev, "erase addr=0x%llx len 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (long long)instr->addr, (long long)instr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) div_u64_rem(instr->len, priv->page_size, &rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (rem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) div_u64_rem(instr->addr, priv->page_size, &rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (rem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) x.tx_buf = command = priv->command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) x.len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spi_message_add_tail(&x, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) while (instr->len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int pageaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int do_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Calculate flash page address; use block erase (for speed) if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * we're at a block boundary and need to erase the whole block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pageaddr = div_u64(instr->addr, priv->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pageaddr = pageaddr << priv->page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) command[1] = (u8)(pageaddr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) command[2] = (u8)(pageaddr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) command[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_dbg(&spi->dev, "ERASE %s: (%x) %x %x %x [%i]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) do_block ? "block" : "page",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) command[0], command[1], command[2], command[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pageaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) status = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (void) dataflash_waitready(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&spi->dev, "erase %x, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pageaddr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* REVISIT: can retry instr->retries times; or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * giveup and instr->fail_addr = instr->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (do_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) instr->addr += blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) instr->len -= blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) instr->addr += priv->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) instr->len -= priv->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Read from the DataFlash device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * from : Start offset in flash device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * len : Amount to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * retlen : About of data actually read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * buf : Buffer containing the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct spi_transfer x[2] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(&priv->spi->dev, "read 0x%x..0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (unsigned int)from, (unsigned int)(from + len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Calculate flash page/byte address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) addr = (((unsigned)from / priv->page_size) << priv->page_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) + ((unsigned)from % priv->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) command = priv->command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(&priv->spi->dev, "READ: (%x) %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) command[0], command[1], command[2], command[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) x[0].tx_buf = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) x[0].len = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spi_message_add_tail(&x[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) x[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) x[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spi_message_add_tail(&x[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Continuous read, max clock = f(car) which may be less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * the peak rate available. Some chips support commands with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * fewer "don't care" bytes. Both buffers stay unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) command[0] = OP_READ_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) command[1] = (u8)(addr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) command[2] = (u8)(addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) command[3] = (u8)(addr >> 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* plus 4 "don't care" bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) status = spi_sync(priv->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *retlen = msg.actual_length - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(&priv->spi->dev, "read %x..%x --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (unsigned)from, (unsigned)(from + len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Write to the DataFlash device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * to : Start offset in flash device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * len : Amount to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * retlen : Amount of data actually written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * buf : Buffer containing the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) size_t * retlen, const u_char * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct spi_device *spi = priv->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct spi_transfer x[2] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int pageaddr, addr, offset, writelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) size_t remaining = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u_char *writebuf = (u_char *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 *command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(&spi->dev, "write 0x%x..0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (unsigned int)to, (unsigned int)(to + len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) x[0].tx_buf = command = priv->command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) x[0].len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spi_message_add_tail(&x[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pageaddr = ((unsigned)to / priv->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) offset = ((unsigned)to % priv->page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (offset + len > priv->page_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writelen = priv->page_size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writelen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) while (remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(&spi->dev, "write @ %i:%i len=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pageaddr, offset, writelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* REVISIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * (a) each page in a sector must be rewritten at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * once every 10K sibling erase/program operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * (b) for pages that are already erased, we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * use WRITE+MWRITE not PROGRAM for ~30% speedup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * (c) WRITE to buffer could be done while waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * a previous MWRITE/MWERASE to complete ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * (d) error handling here seems to be mostly missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Two persistent bits per page, plus a per-sector counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * could support (a) and (b) ... we might consider using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * the second half of sector zero, which is just one block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * to track that state. (On AT91, that sector should also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * support boot-from-DataFlash.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) addr = pageaddr << priv->page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* (1) Maybe transfer partial page to Buffer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (writelen != priv->page_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) command[0] = OP_TRANSFER_BUF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) command[1] = (addr & 0x00FF0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) command[2] = (addr & 0x0000FF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) command[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(&spi->dev, "TRANSFER: (%x) %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) command[0], command[1], command[2], command[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) status = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(&spi->dev, "xfer %u -> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) addr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (void) dataflash_waitready(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* (2) Program full page via Buffer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) addr += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) command[0] = OP_PROGRAM_VIA_BUF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) command[1] = (addr & 0x00FF0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) command[2] = (addr & 0x0000FF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) command[3] = (addr & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_dbg(&spi->dev, "PROGRAM: (%x) %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) command[0], command[1], command[2], command[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) x[1].tx_buf = writebuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) x[1].len = writelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spi_message_add_tail(x + 1, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) status = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spi_transfer_del(x + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(&spi->dev, "pgm %u/%u -> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) addr, writelen, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (void) dataflash_waitready(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* (3) Compare to Buffer1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) addr = pageaddr << priv->page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) command[0] = OP_COMPARE_BUF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) command[1] = (addr & 0x00FF0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) command[2] = (addr & 0x0000FF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) command[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_dbg(&spi->dev, "COMPARE: (%x) %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) command[0], command[1], command[2], command[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) status = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_dbg(&spi->dev, "compare %u -> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) addr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) status = dataflash_waitready(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Check result of the compare operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (status & (1 << 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(&spi->dev, "compare page %u, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pageaddr, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) remaining = remaining - writelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pageaddr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) writebuf += writelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *retlen += writelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (remaining > priv->page_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writelen = priv->page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writelen = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* ......................................................................... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifdef CONFIG_MTD_DATAFLASH_OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int dataflash_get_otp_info(struct mtd_info *mtd, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) size_t *retlen, struct otp_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Report both blocks as identical: bytes 0..64, locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Unless the user block changed from all-ones, we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * tell whether it's still writable; so we assume it isn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) info->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) info->length = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) info->locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *retlen = sizeof(*info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static ssize_t otp_read(struct spi_device *spi, unsigned base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 *buf, loff_t off, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) size_t l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct spi_transfer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (off > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if ((off + len) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) len = 64 - off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) l = 4 + base + off + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) scratch = kzalloc(l, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* OUT: OP_READ_SECURITY, 3 don't-care bytes, zeroes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * IN: ignore 4 bytes, data bytes 0..N (max 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) scratch[0] = OP_READ_SECURITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) memset(&t, 0, sizeof t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) t.tx_buf = scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) t.rx_buf = scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) t.len = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dataflash_waitready(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) status = spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) memcpy(buf, scratch + 4 + base + off, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) status = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) kfree(scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int dataflash_read_fact_otp(struct mtd_info *mtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) loff_t from, size_t len, size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* 64 bytes, from 0..63 ... start at 64 on-chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) status = otp_read(priv->spi, 64, buf, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *retlen = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int dataflash_read_user_otp(struct mtd_info *mtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) loff_t from, size_t len, size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* 64 bytes, from 0..63 ... start at 0 on-chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) status = otp_read(priv->spi, 0, buf, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *retlen = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int dataflash_write_user_otp(struct mtd_info *mtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) loff_t from, size_t len, size_t *retlen, u_char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const size_t l = 4 + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 *scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct spi_transfer t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct dataflash *priv = mtd->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (from >= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Attempting to write beyond the end of OTP memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * no data can be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *retlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Truncate the write to fit into OTP memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if ((from + len) > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) len = 64 - from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* OUT: OP_WRITE_SECURITY, 3 zeroes, 64 data-or-zero bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * IN: ignore all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) scratch = kzalloc(l, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) scratch[0] = OP_WRITE_SECURITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) memcpy(scratch + 4 + from, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) memset(&t, 0, sizeof t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) t.tx_buf = scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) t.len = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spi_message_add_tail(&t, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Write the OTP bits, if they've not yet been written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * This modifies SRAM buffer1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dataflash_waitready(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) status = spi_sync(priv->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) kfree(scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *retlen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static char *otp_setup(struct mtd_info *device, char revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) device->_get_fact_prot_info = dataflash_get_otp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) device->_read_fact_prot_reg = dataflash_read_fact_otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) device->_get_user_prot_info = dataflash_get_otp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) device->_read_user_prot_reg = dataflash_read_user_otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* rev c parts (at45db321c and at45db1281 only!) use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * different write procedure; not (yet?) implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (revision > 'c')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) device->_write_user_prot_reg = dataflash_write_user_otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ", OTP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static char *otp_setup(struct mtd_info *device, char revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return " (OTP)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* ......................................................................... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Register DataFlash device with MTD subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int add_dataflash_otp(struct spi_device *spi, char *name, int nr_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int pagesize, int pageoffset, char revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct dataflash *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct mtd_info *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct flash_platform_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) char *otp_tag = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) priv = kzalloc(sizeof *priv, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) priv->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) priv->page_size = pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) priv->page_offset = pageoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* name must be usable with cmdlinepart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sprintf(priv->name, "spi%d.%d-%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spi->master->bus_num, spi->chip_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) device = &priv->mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) device->name = (pdata && pdata->name) ? pdata->name : priv->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) device->size = nr_pages * pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) device->erasesize = pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) device->writesize = pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) device->type = MTD_DATAFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) device->flags = MTD_WRITEABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) device->_erase = dataflash_erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) device->_read = dataflash_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) device->_write = dataflash_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) device->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) device->dev.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mtd_set_of_node(device, spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (revision >= 'c')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) otp_tag = otp_setup(device, revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_info(&spi->dev, "%s (%lld KBytes) pagesize %d bytes%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) name, (long long)((device->size + 1023) >> 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pagesize, otp_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spi_set_drvdata(spi, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) err = mtd_device_register(device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pdata ? pdata->parts : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pdata ? pdata->nr_parts : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static inline int add_dataflash(struct spi_device *spi, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int nr_pages, int pagesize, int pageoffset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return add_dataflash_otp(spi, name, nr_pages, pagesize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pageoffset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct flash_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* JEDEC id has a high byte of zero plus three data bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * the manufacturer id, then a two byte device id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u64 jedec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* The size listed here is what works with OP_ERASE_PAGE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u16 pagesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u16 pageoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SUP_EXTID 0x0004 /* supports extended ID data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct flash_info dataflash_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * one with IS_POW2PS and the other without. The entry with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * non-2^N byte page size can't name exact chip revisions without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * losing backwards compatibility for cmdlinepart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * These newer chips also support 128-byte security registers (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * 64 bytes one-time-programmable) and software write-protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { "AT45DB641E", 0x1f28000100ULL, 32768, 264, 9, SUP_EXTID | SUP_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { "at45db641e", 0x1f28000100ULL, 32768, 256, 8, SUP_EXTID | SUP_POW2PS | IS_POW2PS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct flash_info *jedec_lookup(struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u64 jedec, bool use_extid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct flash_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) for (info = dataflash_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) info < dataflash_data + ARRAY_SIZE(dataflash_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) info++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (use_extid && !(info->flags & SUP_EXTID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (info->jedec_id == jedec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_dbg(&spi->dev, "OTP, sector protect%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) (info->flags & SUP_POW2PS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ", binary pagesize" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (info->flags & SUP_POW2PS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) status = dataflash_status(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_dbg(&spi->dev, "status error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return ERR_PTR(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (status & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (info->flags & IS_POW2PS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!(info->flags & IS_POW2PS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct flash_info *jedec_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u8 code = OP_READ_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u64 jedec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 id[sizeof(jedec)] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) const unsigned int id_size = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct flash_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * JEDEC also defines an optional "extended device information"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * string for after vendor-specific data, after the three bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * we use here. Supporting some chips might require using it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * That's not an error; only rev C and newer chips handle it, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * only Atmel sells these chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = spi_write_then_read(spi, &code, 1, id, id_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_dbg(&spi->dev, "error %d reading JEDEC ID\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (id[0] != CFI_MFR_ATMEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) jedec = be64_to_cpup((__be64 *)id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * First, try to match device using extended device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_EXTID, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!IS_ERR(info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * If that fails, make another pass using regular ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_ID, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!IS_ERR(info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Treat other chips as errors ... we won't know the right page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * size (it might be binary) even when we can tell which density
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * class is involved (legacy chip id scheme).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_warn(&spi->dev, "JEDEC id %016llx not handled\n", jedec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * or else the ID code embedded in the status bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * Device Density ID code #Pages PageSize Offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int dataflash_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct flash_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Try to detect dataflash by JEDEC ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * If it succeeds we know we have either a C or D part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * D will support power of 2 pagesize option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * Both support the security register, though with different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * write procedures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) info = jedec_probe(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (IS_ERR(info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return PTR_ERR(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (info != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return add_dataflash_otp(spi, info->name, info->nr_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) info->pagesize, info->pageoffset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) (info->flags & SUP_POW2PS) ? 'd' : 'c');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Older chips support only legacy commands, identifing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * capacity using bits in the status byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) status = dataflash_status(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (status <= 0 || status == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(&spi->dev, "status error %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (status == 0 || status == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) status = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* if there's a device there, assume it's dataflash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * board setup should have set spi->max_speed_max to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * match f(car) for continuous reads, mode 0 or 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) switch (status & 0x3c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case 0x0c: /* 0 0 1 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) status = add_dataflash(spi, "AT45DB011B", 512, 264, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case 0x14: /* 0 1 0 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case 0x1c: /* 0 1 1 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case 0x24: /* 1 0 0 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case 0x2c: /* 1 0 1 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case 0x34: /* 1 1 0 1 x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case 0x38: /* 1 1 1 x x x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case 0x3c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* obsolete AT45DB1282 not (yet?) supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_info(&spi->dev, "unsupported device (%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) status & 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) status = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_dbg(&spi->dev, "add_dataflash --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int dataflash_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct dataflash *flash = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_dbg(&spi->dev, "remove\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) status = mtd_device_unregister(&flash->mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) kfree(flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct spi_driver dataflash_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .name = "mtd_dataflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .of_match_table = of_match_ptr(dataflash_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .probe = dataflash_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .remove = dataflash_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* FIXME: investigate suspend and resume... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) module_spi_driver(dataflash_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) MODULE_AUTHOR("Andrew Victor, David Brownell");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MODULE_DESCRIPTION("MTD DataFlash driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) MODULE_ALIAS("spi:mtd_dataflash");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags