^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2001, 2003 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * DECstation/DECsystem 5000/2x0 and DECsystem 5900 and 5900/260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Addresses are decoded as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 0x000000 - 0x3fffff SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 0x400000 - 0x7fffff CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Within the SRAM area the following ranges are forced by the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 0x000400 - ENDofRAM storage area, available to operating systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * but we can't really use the available area right from 0x000400 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the first word is used by the firmware as a status flag passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * from an operating system. If anything but the valid data magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ID value is found, the firmware considers the SRAM clean, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * containing no valid data, and disables the battery resulting in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * data being erased as soon as power is switched off. So the choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * for the start address of the user-available is 0x001000 which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * nicely page aligned. The area between 0x000404 and 0x000fff may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * be used by the driver for own needs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The diagnostic area defines two status words to be read by an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * operating system, a magic ID to distinguish a MS02-NV board from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * anything else and a status information providing results of tests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * as well as the size of SRAM available, which can be 1MiB or 2MiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * (that's what the firmware handles; no idea if 2MiB modules ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * existed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The firmware only handles the MS02-NV board if installed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * last (15th) slot, so for any other location the status information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * stored in the SRAM cannot be relied upon. But from the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * point of view there is no problem using up to 14 such boards in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * system -- only the 1st slot needs to be filled with a DRAM module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * The MS02-NV board is ECC-protected, like other MS02 memory boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The state of the battery as provided by the CSR is reflected on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * the two onboard LEDs. When facing the battery side of the board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * with the LEDs at the top left and the battery at the bottom right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * (i.e. looking from the back side of the system box), their meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * is as follows (the system has to be powered on):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * left LED battery disable status: lit = enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * right LED battery condition status: lit = OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* MS02-NV iomem register offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MS02NV_CSR 0x400000 /* control & status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* MS02-NV CSR status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MS02NV_CSR_BATT_OK 0x01 /* battery OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MS02NV_CSR_BATT_OFF 0x02 /* battery disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* MS02-NV memory offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MS02NV_DIAG 0x0003f8 /* diagnostic status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MS02NV_MAGIC 0x0003fc /* MS02-NV magic ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MS02NV_VALID 0x000400 /* valid data magic ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MS02NV_RAM 0x001000 /* user-exposed RAM start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* MS02-NV diagnostic status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MS02NV_DIAG_SIZE_SHIFT 0x10 /* SRAM size shift (left) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* MS02-NV general constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MS02NV_ID 0x03021966 /* MS02-NV magic ID value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MS02NV_VALID_ID 0xbd100248 /* valid data magic ID value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MS02NV_SLOT_SIZE 0x800000 /* size of the address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) decoded by the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) typedef volatile u32 ms02nv_uint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ms02nv_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mtd_info *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct resource *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct resource *diag_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct resource *user_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct resource *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u_char *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u_char *uaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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