^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mchp23k256.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Microchip 23k256 SPI RAM chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright © 2016 Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX_CMD_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mchp23_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mchp23k256_flash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mtd_info mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const struct mchp23_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCHP23K256_CMD_WRITE_STATUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCHP23K256_CMD_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCHP23K256_CMD_READ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MCHP23K256_MODE_SEQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define to_mchp23k256_flash(x) container_of(x, struct mchp23k256_flash, mtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int addr, u8 *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Address is sent in big endian (MSB first) and we skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * the first entry of the cmd array which contains the cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cmd[i] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int mchp23k256_cmdsz(struct mchp23k256_flash *flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 1 + flash->caps->addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int mchp23k256_write(struct mtd_info *mtd, loff_t to, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) size_t *retlen, const unsigned char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct spi_transfer transfer[2] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned char command[MAX_CMD_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ret, cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cmd_len = mchp23k256_cmdsz(flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) command[0] = MCHP23K256_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mchp23k256_addr2cmd(flash, to, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) transfer[0].tx_buf = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) transfer[0].len = cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spi_message_add_tail(&transfer[0], &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) transfer[1].tx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) transfer[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spi_message_add_tail(&transfer[1], &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mutex_lock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = spi_sync(flash->spi, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (retlen && message.actual_length > cmd_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *retlen += message.actual_length - cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int mchp23k256_read(struct mtd_info *mtd, loff_t from, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) size_t *retlen, unsigned char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct spi_transfer transfer[2] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char command[MAX_CMD_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int ret, cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cmd_len = mchp23k256_cmdsz(flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) memset(&transfer, 0, sizeof(transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) command[0] = MCHP23K256_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mchp23k256_addr2cmd(flash, from, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) transfer[0].tx_buf = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) transfer[0].len = cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spi_message_add_tail(&transfer[0], &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) transfer[1].rx_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) transfer[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spi_message_add_tail(&transfer[1], &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mutex_lock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = spi_sync(flash->spi, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mutex_unlock(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (retlen && message.actual_length > cmd_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *retlen += message.actual_length - cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Set the device into sequential mode. This allows read/writes to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * entire SRAM in a single operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int mchp23k256_set_mode(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct spi_transfer transfer = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char command[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) command[0] = MCHP23K256_CMD_WRITE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) command[1] = MCHP23K256_MODE_SEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) transfer.tx_buf = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) transfer.len = sizeof(command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spi_message_add_tail(&transfer, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return spi_sync(spi, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct mchp23_caps mchp23k256_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .size = SZ_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .addr_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct mchp23_caps mchp23lcv1024_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .addr_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int mchp23k256_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct mchp23k256_flash *flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct flash_platform_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) flash->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mutex_init(&flash->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) spi_set_drvdata(spi, flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err = mchp23k256_set_mode(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) data = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) flash->caps = of_device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!flash->caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) flash->caps = &mchp23k256_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mtd_set_of_node(&flash->mtd, spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) flash->mtd.dev.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) flash->mtd.type = MTD_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) flash->mtd.flags = MTD_CAP_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) flash->mtd.writesize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) flash->mtd.size = flash->caps->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) flash->mtd._read = mchp23k256_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) flash->mtd._write = mchp23k256_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) err = mtd_device_register(&flash->mtd, data ? data->parts : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data ? data->nr_parts : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mchp23k256_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct mchp23k256_flash *flash = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return mtd_device_unregister(&flash->mtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct of_device_id mchp23k256_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .compatible = "microchip,mchp23k256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .data = &mchp23k256_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .compatible = "microchip,mchp23lcv1024",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .data = &mchp23lcv1024_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct spi_driver mchp23k256_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "mchp23k256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .of_match_table = of_match_ptr(mchp23k256_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .probe = mchp23k256_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .remove = mchp23k256_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) module_spi_driver(mchp23k256_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DESCRIPTION("MTD SPI driver for MCHP23K256 RAM chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_AUTHOR("Andrew Lunn <andre@lunn.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_ALIAS("spi:mchp23k256");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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