^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __BCM47XXSFLASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __BCM47XXSFLASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BCM47XXSFLASH_WINDOW_SZ SZ_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Used for ST flashes only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define OPCODE_ST_WREN 0x0006 /* Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OPCODE_ST_WRDIS 0x0004 /* Write Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OPCODE_ST_RDSR 0x0105 /* Read Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OPCODE_ST_WRSR 0x0101 /* Write Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OPCODE_ST_READ 0x0303 /* Read Data Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OPCODE_ST_PP 0x0302 /* Page Program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OPCODE_ST_SE 0x02d8 /* Sector Erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OPCODE_ST_BE 0x00c7 /* Bulk Erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OPCODE_ST_DP 0x00b9 /* Deep Power-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OPCODE_ST_RES 0x03ab /* Read Electronic Signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OPCODE_ST_CSA 0x1000 /* Keep chip select asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OPCODE_ST_SSE 0x0220 /* Sub-sector Erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OPCODE_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte addressing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Used for Atmel flashes only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OPCODE_AT_READ 0x07e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OPCODE_AT_PAGE_READ 0x07d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OPCODE_AT_STATUS 0x01d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OPCODE_AT_BUF1_WRITE 0x0384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OPCODE_AT_BUF2_WRITE 0x0387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OPCODE_AT_BUF1_ERASE_PROGRAM 0x0283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OPCODE_AT_BUF2_ERASE_PROGRAM 0x0286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OPCODE_AT_BUF1_PROGRAM 0x0288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OPCODE_AT_BUF2_PROGRAM 0x0289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OPCODE_AT_PAGE_ERASE 0x0281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OPCODE_AT_BLOCK_ERASE 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OPCODE_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OPCODE_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OPCODE_AT_BUF1_LOAD 0x0253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OPCODE_AT_BUF2_LOAD 0x0255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OPCODE_AT_BUF1_COMPARE 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OPCODE_AT_BUF2_COMPARE 0x0261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OPCODE_AT_BUF1_REPROGRAM 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OPCODE_AT_BUF2_REPROGRAM 0x0259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Status register bits for ST flashes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SR_ST_WIP 0x01 /* Write In Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SR_ST_WEL 0x02 /* Write Enable Latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SR_ST_BP_MASK 0x1c /* Block Protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SR_ST_BP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SR_ST_SRWD 0x80 /* Status Register Write Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Status register bits for Atmel flashes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SR_AT_READY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SR_AT_MISMATCH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SR_AT_ID_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SR_AT_ID_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct bcma_drv_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum bcm47xxsflash_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BCM47XXSFLASH_TYPE_ATMEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BCM47XXSFLASH_TYPE_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct bcm47xxsflash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct bcma_drv_cc *bcma_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int (*cc_read)(struct bcm47xxsflash *b47s, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void (*cc_write)(struct bcm47xxsflash *b47s, u16 offset, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum bcm47xxsflash_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 numblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mtd_info mtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* BCM47XXSFLASH */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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