Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define LOCK_CODE		0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define WBSD_CONF_SWRST		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define WBSD_CONF_DEVICE	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define WBSD_CONF_ID_HI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define WBSD_CONF_ID_LO		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define WBSD_CONF_POWER		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define WBSD_CONF_PME		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define WBSD_CONF_PMES		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define WBSD_CONF_ENABLE	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define WBSD_CONF_PORT_HI	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define WBSD_CONF_PORT_LO	0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WBSD_CONF_IRQ		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WBSD_CONF_DRQ		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WBSD_CONF_PINS		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DEVICE_SD		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WBSD_PINS_DAT3_HI	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WBSD_PINS_DAT3_OUT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WBSD_PINS_GP11_HI	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define WBSD_PINS_DETECT_GP11	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define WBSD_PINS_DETECT_DAT3	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WBSD_CMDR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WBSD_DFR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WBSD_EIR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WBSD_ISR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WBSD_FSR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WBSD_IDXR		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WBSD_DATAR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WBSD_CSR		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WBSD_EINT_CARD		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WBSD_EINT_FIFO_THRE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WBSD_EINT_CRC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WBSD_EINT_TIMEOUT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WBSD_EINT_PROGEND	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WBSD_EINT_BUSYEND	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WBSD_EINT_TC		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WBSD_INT_PENDING	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WBSD_INT_CARD		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WBSD_INT_FIFO_THRE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WBSD_INT_CRC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WBSD_INT_TIMEOUT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WBSD_INT_PROGEND	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WBSD_INT_BUSYEND	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WBSD_INT_TC		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WBSD_FIFO_EMPTY		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WBSD_FIFO_FULL		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WBSD_FIFO_EMTHRE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WBSD_FIFO_FUTHRE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define WBSD_FIFO_SZMASK	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WBSD_MSLED		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WBSD_POWER_N		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define WBSD_WRPT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WBSD_CARDPRESENT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WBSD_IDX_CLK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WBSD_IDX_PBSMSB		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WBSD_IDX_TAAC		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WBSD_IDX_NSAC		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WBSD_IDX_PBSLSB		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WBSD_IDX_SETUP		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WBSD_IDX_DMA		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WBSD_IDX_FIFOEN		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WBSD_IDX_STATUS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WBSD_IDX_RSPLEN		0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WBSD_IDX_RESP0		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define WBSD_IDX_RESP1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define WBSD_IDX_RESP2		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WBSD_IDX_RESP3		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WBSD_IDX_RESP4		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WBSD_IDX_RESP5		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define WBSD_IDX_RESP6		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define WBSD_IDX_RESP7		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define WBSD_IDX_RESP8		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define WBSD_IDX_RESP9		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define WBSD_IDX_RESP10		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WBSD_IDX_RESP11		0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define WBSD_IDX_RESP12		0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define WBSD_IDX_RESP13		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define WBSD_IDX_RESP14		0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define WBSD_IDX_RESP15		0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define WBSD_IDX_RESP16		0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define WBSD_IDX_CRCSTATUS	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define WBSD_IDX_ISR		0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WBSD_CLK_375K		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WBSD_CLK_12M		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WBSD_CLK_16M		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WBSD_CLK_24M		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WBSD_DATA_WIDTH		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WBSD_DAT3_H		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WBSD_FIFO_RESET		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WBSD_SOFT_RESET		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WBSD_INC_INDEX		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WBSD_DMA_SINGLE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WBSD_DMA_ENABLE		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WBSD_FIFOEN_EMPTY	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WBSD_FIFOEN_FULL	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WBSD_FIFO_THREMASK	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WBSD_BLOCK_READ		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WBSD_BLOCK_WRITE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WBSD_BUSY		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WBSD_CARDTRAFFIC	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WBSD_SENDCMD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WBSD_RECVRES		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WBSD_RSP_SHORT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define WBSD_RSP_LONG		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define WBSD_CRC_MASK		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WBSD_CRC_OK		0x05 /* S010E (00101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WBSD_CRC_FAIL		0x0B /* S101E (01011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define WBSD_DMA_SIZE		65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct wbsd_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct mmc_host*	mmc;		/* MMC structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	spinlock_t		lock;		/* Mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int			flags;		/* Driver states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WBSD_FCARD_PRESENT	(1<<0)		/* Card is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WBSD_FIGNORE_DETECT	(1<<1)		/* Ignore card detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct mmc_request*	mrq;		/* Current request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u8			isr;		/* Accumulated ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct scatterlist*	cur_sg;		/* Current SG entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned int		num_sg;		/* Number of entries left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned int		offset;		/* Offset into current entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned int		remain;		/* Data left in curren entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	char*			dma_buffer;	/* ISA DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	dma_addr_t		dma_addr;	/* Physical address for same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int			firsterr;	/* See fifo functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u8			clk;		/* Current clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned char		bus_width;	/* Current bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int			config;		/* Config port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8			unlock_code;	/* Code to unlock config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int			chip_id;	/* ID of controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int			base;		/* I/O port base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int			irq;		/* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int			dma;		/* DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct tasklet_struct	fifo_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct tasklet_struct	crc_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct tasklet_struct	timeout_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct tasklet_struct	finish_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct timer_list	ignore_timer;	/* Ignore detection timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };