^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Toshiba PCI Secure Digital Host Controller Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Ondrej Zary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Richard Betts, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HCLK 33000000 /* 33 MHz (PCI clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SD_PCICFG_CLKSTOP 0x40 /* 0x1f = clock controller, 0 = stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SD_PCICFG_CLKMODE 0x42 /* Control clock of SD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SD_PCICFG_PINSTATUS 0x44 /* R/O: read status of SD pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SD_PCICFG_POWER1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SD_PCICFG_POWER2 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SD_PCICFG_POWER3 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SD_PCICFG_CARDDETECT 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SD_PCICFG_SLOTS 0x50 /* R/O: define support slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SD_PCICFG_SDLED_ENABLE1 0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SD_PCICFG_SDLED_ENABLE2 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SD_PCICFG_CLKSTOP_ENABLE_ALL 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SD_PCICFG_LED_ENABLE1_START 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SD_PCICFG_LED_ENABLE2_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SD_PCICFG_PWR1_33V 0x08 /* Set for 3.3 volts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SD_PCICFG_PWR2_AUTO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SD_CMD 0x00 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SD_ARG0 0x04 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SD_ARG1 0x06 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SD_STOPINTERNAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SD_BLOCKCOUNT 0x0a /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SD_RESPONSE0 0x0c /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SD_RESPONSE1 0x0e /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SD_RESPONSE2 0x10 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SD_RESPONSE3 0x12 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SD_RESPONSE4 0x14 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SD_RESPONSE5 0x16 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SD_RESPONSE6 0x18 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SD_RESPONSE7 0x1a /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SD_CARDSTATUS 0x1c /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SD_BUFFERCTRL 0x1e /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SD_INTMASKCARD 0x20 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SD_INTMASKBUFFER 0x22 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SD_CARDCLOCKCTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SD_CARDXFERDATALEN 0x26 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SD_CARDOPTIONSETUP 0x28 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SD_ERRORSTATUS0 0x2c /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SD_ERRORSTATUS1 0x2e /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SD_DATAPORT 0x30 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SD_TRANSACTIONCTRL 0x34 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SD_SOFTWARERESET 0xe0 /* also for SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* registers above marked "also for SDIO" and all SDIO registers below can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * accessed at SDIO_BASE + reg address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDIO_BASE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDIO_CARDPORTSEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDIO_CARDINTCTRL 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDIO_CLOCKNWAITCTRL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDIO_HOSTINFORMATION 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDIO_ERRORCTRL 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDIO_LEDCTRL 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SD_TRANSCTL_SET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SD_CARDCLK_DIV_DISABLE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SD_CARDCLK_ENABLE_CLOCK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SD_CARDCLK_CLK_DIV_512 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SD_CARDCLK_CLK_DIV_256 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SD_CARDCLK_CLK_DIV_128 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SD_CARDCLK_CLK_DIV_64 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SD_CARDCLK_CLK_DIV_32 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SD_CARDCLK_CLK_DIV_16 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SD_CARDCLK_CLK_DIV_8 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SD_CARDCLK_CLK_DIV_4 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SD_CARDCLK_CLK_DIV_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SD_CARDOPT_REQUIRED 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SD_CARDOPT_DATA_RESP_TIMEOUT(x) (((x) & 0x0f) << 4) /* 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SD_CARDOPT_C2_MODULE_ABSENT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SD_CARDOPT_DATA_XFR_WIDTH_1 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SD_CARDOPT_DATA_XFR_WIDTH_4 (0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SD_CMD_TYPE_CMD (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SD_CMD_TYPE_ACMD (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SD_CMD_TYPE_AUTHEN (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SD_CMD_RESP_TYPE_NONE (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SD_CMD_RESP_TYPE_EXT_R1 (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SD_CMD_RESP_TYPE_EXT_R1B (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SD_CMD_RESP_TYPE_EXT_R2 (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SD_CMD_RESP_TYPE_EXT_R3 (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SD_CMD_RESP_TYPE_EXT_R6 (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SD_CMD_RESP_TYPE_EXT_R7 (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SD_CMD_DATA_PRESENT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SD_CMD_TRANSFER_READ BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SD_CMD_MULTI_BLOCK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SD_CMD_SECURITY_CMD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SD_STOPINT_ISSUE_CMD12 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SD_CARD_RESP_END BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SD_CARD_RW_END BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SD_CARD_CARD_REMOVED_0 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SD_CARD_CARD_INSERTED_0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SD_CARD_PRESENT_0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SD_CARD_UNK6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SD_CARD_WRITE_PROTECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SD_CARD_CARD_REMOVED_3 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SD_CARD_CARD_INSERTED_3 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SD_CARD_PRESENT_3 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SD_BUF_CMD_INDEX_ERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SD_BUF_CRC_ERR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SD_BUF_STOP_BIT_END_ERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SD_BUF_DATA_TIMEOUT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SD_BUF_OVERFLOW BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SD_BUF_UNDERFLOW BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SD_BUF_CMD_TIMEOUT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SD_BUF_UNK7 BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SD_BUF_READ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SD_BUF_WRITE_ENABLE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SD_BUF_ILLEGAL_FUNCTION BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SD_BUF_CMD_BUSY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SD_BUF_ILLEGAL_ACCESS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SD_ERR0_RESP_CMD_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SD_ERR0_RESP_CMD12_END_BIT_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SD_ERR0_READ_DATA_END_BIT_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SD_ERR0_RESP_NON_CMD12_CRC_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SD_ERR0_RESP_CMD12_CRC_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SD_ERR0_READ_DATA_CRC_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SD_ERR0_WRITE_CMD_CRC_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SD_ERR1_NO_CMD_RESP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SD_ERR1_TIMEOUT_READ_DATA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SD_ERR1_TIMEOUT_CRS_STATUS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SD_ERR1_TIMEOUT_CRC_BUSY BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) | SD_CARD_WRITE_PROTECT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) | SD_CARD_UNK6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) | SD_CARD_PRESENT_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) | SD_BUF_UNK7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | SD_BUF_CMD_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct toshsd_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mmc_request *mrq;/* Current request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mmc_command *cmd;/* Current command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mmc_data *data; /* Current data request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct sg_mapping_iter sg_miter; /* for PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __iomem *ioaddr; /* mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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